A Universal Four-Pair Impedance Bridge

Corney, A.C.

doi:10.1109/tim.1979.4314807

Cited by 17 publications

(9 citation statements)

References 5 publications

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“…Its input is the voltage stored in C 2 in the previous cP3 phase. The voltage across C 1 then becomes V(i) given by (2). C 3 is also charged to V(i) through S14 and SI8· This completes one cycle of operation.…”

Section: ) Cps Phasementioning

confidence: 99%

“…4 [5]. It converts the voltage V x produced in the preceding "sample" state into the n-bit binary number b, according to the following algorithm [8]: (2) I;Z S4 SID Sll S12 S13 S14 SIS S16 S17 S18…”

Section: B Operation In the "Convert" Statementioning

confidence: 99%

“…The analog arithmetic circuit executes the operation involved in (2), while, operating also as a comparator, the S/H circuit executes the operation involved in (3). Switching sequence for executing the conversion algorithm is listed in Table II.…”

Section: B Operation In the "Convert" Statementioning

confidence: 99%

“…In the ith cycle of operation, V(i) given by (2) is produced by the following steps. (Refer also to Table II to identify the operation in each step.)…”

Section: B Operation In the "Convert" Statementioning

confidence: 99%

“…Conventional methods using Schering, transformer-ratio arm, or four-terminalpair bridge are useful for the measurement of discrete capacitors [1], [2]. They are, however, not applicable to integrated MOS capacitors, because they cannot separate contributions of parasitic capacitances.…”

Section: Introductionmentioning

confidence: 99%

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A switched-capacitor digital capacitance meter

Matsumoto

Watanabe

1986

IEEE Trans. Instrum. Meas.

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A digital capacitance meter has been developed based on the switched-capacitor cyclic analog-to-digital (A/D) converter. It consists of the analog arithmetic and sample/hold (S/H) circuits. The arithmetic circuit first samples the capacitance to be measured in a form of its proportional voltage. This voltage is then converted into a binary number by the A/D converter. The whole operation is insensitive to parasitic capacitances, offset voltages of op amps, and the capacitance mismatch involved in the circuit. Therefore, the proposed meter permits an accurate capacitance measurement. Error analysis shows that 12-bit accuracy can be expected by realizing the meter in an Ie form. A prototype meter built using discrete components and examples of measurement are also given.

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Section: ) Cps Phasementioning

confidence: 99%

Section: B Operation In the "Convert" Statementioning

confidence: 99%

Section: B Operation In the "Convert" Statementioning

confidence: 99%

“…In the ith cycle of operation, V(i) given by (2) is produced by the following steps. (Refer also to Table II to identify the operation in each step.)…”

Section: B Operation In the "Convert" Statementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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