A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications

High-frequency characterization of on-chip digital interconnects

“…The conventional aluminum-silicon dioxide interconnect scheme has been considered a serious limitation to further scaling [1]. This has prompted an industry-wide shift from aluminum to copper interconnects to reduce the resistance, and a relentless search for a reliable low-permittivity dielectric material to reduce the capacitance [2], [3]. However, for wide lines and buses, resistance B. Kleveland is with Matrix Semiconductor, Santa Clara, CA 95054 USA (e-mail: bendik@matrixsemi.com).…”

<title>Impact of subwavelength CD tolerance on device performance</title>

“…Fig.2 shows a growing disparity between CD and λ, both shrinking in accordance with the SIA roadmap [1]. Designs for 100 nm technologies are currently reaching the limit of 248 nm lithography forcing the process to choose between switching to 193 nm steppers or extensively using resolution enhancement techniques (RET): phase shift (PSM) and other complex optical proximity correction (OPC) [2][3][4][5][6]. While the former solution suffers from substantial equipment cost, the latter bears a risk of limited lifetime [7].…”

“…Fig.4. Image qualification for MOSFET endcaps inside a 6T SRAM cell [2][3][4][5][6]: a) layout with OPC hammerhead on an FET endcap, b) proposed tolerance contours for two adjacent cell FETs, c) simulated intensity contours, difficult to qualify without tolerance contours, d) qualification becomes easy due to the introduction of tolerance contours, e) intensity contour simulation with defocus makes it almost impossible to judge layout quality, f) intensity contours simulated with defocus do not meet tolerance criteria, showing that OPC features need optimization, g) same tolerance criteria would necessitate different OPC corrections when poly proximity line is removed, h) the effect of defocus on poly proximity can be easily identified by referring to tolerance lines.…”

High-performance interconnects: an integration overview

“…Power dissipation for receivers, and, to a lesser extent, transmitters can be prohibitively large. However, there is growing evidence that the power required per optical channel, i.e., one transmitter (or modulator) and one receiver connected via free-space may dissipate less than 6 mW of power [30] with circuits that are quite small (e.g., 17 18 m in area). Other issues with optical interconnects are the technologies for fabricating III-V devices on silicon.…”

“…Thus, for a fixed resistance per unit length, thinner metal could be used for copper versus aluminum wiring and sidewall capacitance could be reduced. Later introduction of low-dielectrics relieved sidewall capacitance [12]- [17] and provided more latitude in the optimization of RC, power, and crosstalk versus metal thickness and spacing.…”