A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25-μm CMOS

Yavari, Mohammad; Shoaei, O.; Afzali-Kusha, Ali

doi:10.1109/iscas.2003.1205746

Cited by 3 publications

(1 citation statement)

References 9 publications

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“…After considering circuit stability and spectral tone rejection, a 2-1 cascaded architecture was adopted instead of the single-loop architecture. This architecture has advantages compared to the 1-1-1 cascaded topology, as follows: first, it is unconditionally stable if all of its stages are unconditionally stable, as are the case for the second and first order stages; second, the use of second order noise shaping in the first stage of the cascade avoids the potential presence of discrete noise tones in the overall cascade output, which is desirable for high performance audio applications; third, it is less sensitive to component mismatch [3,4], especially when the feature size is scaled down to 65 nm, where the circuit faces ever greater challenges of variability and reliability.…”

Section: Modulator Architecturementioning

confidence: 99%

A 65-nm low-power high-linearity ΣΔ ADC for audio applications

Lü

Sun

Han

et al. 2013

Sci. China Inf. Sci.

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This paper presents a low-power high linearity Σ∆ analog-to-digital converter (ADC) for audio applications. By adopting low noise large output swing operational amplifiers in a 2-1 cascaded modulator, not only can the noise floor be reduced, but the input signal range can also be enlarged. A low-power, area-efficient digital decimation filter was also designed to decrease the area and the power cost. The ADC was fabricated in the SMIC 65 nm single-poly-eight-metal (1P8M) mixed-signal complementary metal-oxide-semiconductor (CMOS) process with a die area of 0.36 mm 2 . Measurement results showed that a 90 dB peak signal to noise plus distortion ratio (SNDR) and a 93 dB dynamic range (DR) were achieved over the 22.05 kHz audio band. The power dissipation was 2.2 mW from 1.2 V power supply, which is suitable for audio codec applications.

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Section: Modulator Architecturementioning

confidence: 99%

A 65-nm low-power high-linearity ΣΔ ADC for audio applications

Lü

Sun

Han

et al. 2013

Sci. China Inf. Sci.

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A high-performance, low-power σ Δ ADC for digital audio applications

et al. 2010

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A high-performance low-power † analog-to-digital converter (ADC) for digital audio applications is described. It consists of a 2-1 cascaded † modulator and a decimation filter. Various design optimizations are implemented in the system design, circuit implementation and layout design, including a high-overload-level coefficientoptimized modulator architecture, a power-efficient class A/AB operational transconductance amplifier, as well as a multi-stage decimation filter conserving area and power consumption. The ADC is implemented in the SMIC 0.18-m CMOS mixed-signal process. The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm 2 , which dissipates only 2.1 mA quiescent current in the analog circuits.

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Sigma Delta Modulator Design Automation

Hsieh

Chiu

2007

2007 International Conference on Communications, Circuits and Systems

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A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25-μm CMOS

Cited by 3 publications

References 9 publications

A 65-nm low-power high-linearity ΣΔ ADC for audio applications

A 65-nm low-power high-linearity ΣΔ ADC for audio applications

A high-performance, low-power σ Δ ADC for digital audio applications

Sigma Delta Modulator Design Automation

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