A virtual channel network-on-chip for GT and BE traffic

Kavaldjiev, N.K.; Smit, Gerard J. M.; Jansen, P.G.; Wolkotte, P.T.

doi:10.1109/isvlsi.2006.13

Cited by 45 publications

(29 citation statements)

References 16 publications

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“…In [39], Hansson et al provide the latency and throughput guarantees based on the approach of data flow analysis technique, determining required buffer size at network interfaces, which is applicable to the AEthereal NoC. Many other works have been published with variations over these basic ideas [40], [41], [42], [43], [44], [45], [46], [47], [48], [49].…”

Section: Related Workmentioning

confidence: 99%

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Rahmati

Murali

Benini³

et al. 2013

IEEE Trans. Comput.

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Abstract-Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst case bandwidth and latency bounds for RT traffic streams on wormhole-switched NoCs with arbitrary topology. The proposed methods apply to best-effort NoC architectures, with no extra hardware dedicated to RT traffic support. By applying our methods to several realistic NoC designs, we show substantial improvements (more than 30 percent in bandwidth and 50 percent in latency, on average) in bound tightness with respect to existing approaches.

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Section: Related Workmentioning

confidence: 99%

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Rahmati

Murali

Benini³

et al. 2013

IEEE Trans. Comput.

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“…QoS is commonly achieved by providing each traffic class with a separate virtual channel, either in a time-division multiplexing [19,32] or dynamic virtual channel allocation [23,24] manner. Networks providing guaranteed throughput (GT) and best effort (BE) services use VC reservation methodology.…”

Section: Qos Provisionmentioning

confidence: 99%

“…The former is described in Algorithm 1, all buffers are shared by all traffic including GT and BE. For resource reservation solution, one or multiple buffers are dedicated to GT traffic and others are assigned to BE traffic [24].…”

Section: Dynamic Congestion-aware Router Architecturementioning

confidence: 99%

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

Wang

Bagherzadeh

2014

Microprocessors and Microsystems

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a b s t r a c tThis paper proposes a novel QoS-aware and congestion-aware Network-on-Chip architecture that not only enables quality-oriented network transmission and maintains a feasible implementation cost but also well balance traffic load inside the network to enhance overall throughput. By differentiating application traffic into different service classes, bandwidth allocation is managed accordingly to fulfill QoS requirements. Incorporating with congestion control scheme which consists of dynamic arbitration and adaptive routing path selection, high priority traffic is directed to less congested areas and is given preference to available resources. Simulation results show that average latency of high priority and overall traffic is improved dramatically for various traffic patterns. Cost evaluation results also show that the proposed router architecture requires negligible cost overhead but provides better performance for both advanced mesh NoC platforms.

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“…Kavaldjiev et al [15] present a round-robin approach to schedule real-time services on the system. Bjerregaard and Sparso [16] propose a prioritybased round-robin technique to bound latency and bandwidth.…”

Section: A Architectural Considerationsmentioning

confidence: 99%

Network-on-Chip aware scheduling of hard-real-time tasks

Shekhar

Ramaprasad

Mueller

2014

Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems (SIES 2014)

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Abstract-As real-time systems continue to integrate more and more functionality, powerful multi-core architectures are the only viable solution to meet their computational demands under reasonable energy budgets. Dramatic increases in the number of cores on multi-core architectures have led to scalability issues. Modern platforms are moving away from designs with shared caches and shared buses to designs with private caches on cores and high-bandwidth Networks-on-Chip (NoC) for communication. On such architectures, worst-case execution times of real-time tasks depend on the physical location of cores and interference on the NoC. In this paper, we present a dynamic-priority policy for scheduling memory accesses on the NoC and a location-aware partitioning policy that takes explicit advantage of this NoC scheduling policy to improve the efficiency of task allocation. We demonstrate that this combination achieves significant improvement in task set schedulability and NoC utilization.

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A virtual channel network-on-chip for GT and BE traffic

Cited by 45 publications

References 16 publications

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

Network-on-Chip aware scheduling of hard-real-time tasks

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