A VLSI architecture for radix-2/sup k/ Viterbi decoding with transpose algorithm

Abstract

The paper presents a novel transpose path metric (TPM) algoritluii to rcduce tlie interconnection routing complexity for ~1 d i x -2 ~ Viterbi decoder. With simple local interconnections, the algorithm can provide a permutation function for state rcarrangenient in a transpose strategy. With features of modulation and regularity, this algorithm is v e n suitable for VLSI implementation; consequently, a larger memory Icngth VA decoder can be constructed with several siiiallcr mciiiory length modules Finally, a VLSI architecture for 16-states radix-4 VA decoder using TPM lias been developed.