A VLSI implementation of a reconfigurable rational filter

Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

“…The power consumption results refer to the gate-level synthesis of the whole architecture described in Figure 6 (not including the contribution of the clock tree and the I/O pad capacitances) in the 0.18 µm CMOS technology considering a supply voltage of 1.6 V and a temperature of 85 C • . The above results are very interesting when compared to known implementations of nonlinear noise reduction filters [2,6,10,12,13]. The low complexity of the proposed macrocell is also suitable for realization into field programmable gate array (FPGA) technology.…”

“…For the real-time implementation of these techniques several solutions, based on dedicated applied specific integrated circuits (ASIC) technology or software realization for commercial digital signal processors (DSPs) have been proposed [2,6,10,12,13]. The above approaches are typically affected by two main drawbacks.…”

“…An impulsive noise model is also used for faulty bits during coding and transmission or for video scanned from damaged films. To remove meaningless noise information, while preserving fine image details, a large variety of nonlinear filtering methods [2,3,4,5,6,7,8,9,10,11,12] have been proposed in literature since conventional linear filters are known to blur the images. They typically involve weighted averaging masks in case of Gaussian noise or order-statistic filtering in case of impulsive one.…”