A VLSI implementation of a new simultaneous images compression and encryption method

Jridi, Maher; Alfalou, Ayman

doi:10.1109/ist.2010.5548546

Cited by 11 publications

(6 citation statements)

References 9 publications

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“…Only few old compression-encryption systems are implemented using FPGAs, but they do not utilize a strong encryption scheme [45]- [47]. The fastest FPGA implementation is based on the DCT compression and the stream cipher [47]. The stream cipher is not as strong as the block cipher technique, for example the AES-CBC.…”

Section: E Motivations and Objectivesmentioning

confidence: 99%

On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA

et al. 2021

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This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined with the AES to perform the Cipher Block Chaining (CBC) mode. The proposed system is realized using HDL and implemented using Xilinx on XC5VLX50T FPGA. The system has utilized only 25% of the available slices. Furthermore, the system can achieve a throughput of 3.458 Gbps, which is suitable for realtime applications. To validate the compression performance, the system has been tested with all the standard 256×256 images. It is shown that depending on the amount of details in the image, the system can achieve 30dB PSNR at compression ratios in the range of (0.08-0.38). The proposed system can be integrated with digital cameras to process the captured images on-the-fly prior to transmission or storage. Based on the application, the blurred images can be either marked for future enhancement or simply filtered out.

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Section: E Motivations and Objectivesmentioning

confidence: 99%

On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA

et al. 2021

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“…with i ∈ [1,4]. Without loss of generality, we assume that absolute difference between two adjacent vertical pixels do not depend on the position of the pixels in the block.…”

Section: Verificationmentioning

confidence: 99%

“…Without loss of generality, we assume that absolute difference between two adjacent vertical pixels do not depend on the position of the pixels in the block. Consequently, we suppose that dy (i), for i ∈ [1,4], have the same distribution in terms of standard deviation and dynamic range. Hereafter, we use dy for the absolute difference between two adjacent vertical pixels.…”

Section: Verificationmentioning

confidence: 99%

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Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression

Jridi

Alfalou

2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Abstract. The Discrete Cosine Transform (DCT)-based image compression is widely used in today's communication systems. Significant research devoted to this domain has demonstrated that the optical compression methods can offer a higher speed but suffer from bad image quality and a growing complexity. To meet the challenges of higher image quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI architecture of the DCT algorithm and an efficient quantization technique. Our approach is, firstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a reconfigurable quantization method is presented to effectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and comparisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement.

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“…After this optical implementation, in this paper we propose a digital realization of an optimized VLSI for image compression system. This paper is an extension of our prior work [2][3][4] with a new compression scheme along with supplementary simulations and FPGA implementation followed by performance analysis.…”

Section: Introductionmentioning

confidence: 99%

Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT‐Based Image Compression

2012

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The canonical signed digit (CSD) representation of constant coefficients is a unique signed data representation containing the fewest number of nonzero bits. Consequently, for constant multipliers, the number of additions and subtractions is minimized by CSD representation of constant coefficients. This technique is mainly used for finite impulse response (FIR) filter by reducing the number of partial products. In this paper, we use CSD with a novel common subexpression elimination (CSE) scheme on the optimal Loeffler algorithm for the computation of discrete cosine transform (DCT). To meet the challenges of low-power and high-speed processing, we present an optimized image compression scheme based on two-dimensional DCT. Finally, a novel and a simple reconfigurable quantization method combined with DCT computation is presented to effectively save the computational complexity. We present here a new DCT architecture based on the proposed technique. From the experimental results obtained from the FPGA prototype we find that the proposed design has several advantages in terms of power reduction, speed performance, and saving of silicon area along with PSNR improvement over the existing designs as well as the Xilinx core.

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A VLSI implementation of a new simultaneous images compression and encryption method

Cited by 11 publications

References 9 publications

On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA

On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA

Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression

Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT‐Based Image Compression

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