A wideband body-enabled millimeter-wave transceiver for wireless Network-on-Chip

Yu, Xinmin; Sah, Suman P.; Deb, Sujay; Pande, Partha Pratim; Belzer, Benjamin J.; Heo, Deukhyoun

doi:10.1109/mwscas.2011.6026282

Cited by 40 publications

(21 citation statements)

References 17 publications

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“…In designing the on-chip mm-wave wireless transceiver, low power design considerations need to be taken into account both at the architecture and circuit levels. In [18], a noncoherent on-off keying (OOK) based transceiver is designed for an mm-wave WiNoC. OOK is selected as it allows relatively simple and low-power circuit implementation.…”

Section: B Millimeter (Mm)-wavementioning

confidence: 99%

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

Deb

Ganguly

Pande

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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260

152

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Abstract-Current commercial systems-on-chips (SoCs) designs integrate an increasingly large number of predesigned cores and their number is predicted to increase significantly in the near future. For example, molecular-scale computing promises single or even multiple order-of-magnitude improvements in device densities. The network-on-chip (NoC) is an enabling technology for integration of large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of long multi-hop links used in data exchange. The latency, power consumption and interconnect routing problems of conventional NoCs can be addressed by replacing or augmenting multi-hop wired paths with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers. Moreover, as it is an emerging technology, the on-chip wireless links also need to overcome significant challenges pertaining to reliable integration. In this paper, we present various challenges and emerging solutions regarding the design of an efficient and reliable WiNoC architecture.

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Section: B Millimeter (Mm)-wavementioning

confidence: 99%

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

Deb

Ganguly

Pande

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

Self Cite

260

152

View full text Add to dashboard Cite

show abstract

“…Consequently, WiNoCs have been proposed to exploit both the global performance benefits of mm-wave, as well as the short range low power and area benefits of the wireline communication fabric in NoCs. However, the wireless communication fabric is lossy and hence lowers the overall reliability of WiNoCs [45,46].…”

Section: Millimetre-wave Vs Surface Wave-enabled Winocsmentioning

confidence: 99%

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Agyeman

Zong

Yakovlev

et al. 2017

JLPEA

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Abstract:To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications' execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45% (or 50%) in 3D NoCs (or WiNoCs).

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“…Consequently, WiNoCs have been proposed to exploit both the global performance benefits of mm-Wave as well as the short range low power and area benefits of the wireline communication fabric in NoCs. However the wireless communication fabric is lossy with reduced reliability [2], [3]. Surface wave communication has been recently demonstrated as a feasible wireless NoC solution with improved global data transmission, low-power and high bandwidth [1], [4].…”

Section: A Surface Wave Enabled Winocs Architecturesmentioning

confidence: 99%

Towards the practical design of performance-aware resilient wireless NoC architectures

Agyeman

Zong

Kanakis

et al. 2017

2017 7th International Conference on Cloud Computing, Data Science &Amp; Engineering - Confluence

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Abstract-Recently, an improved surface wave-enabled communication fabric has been proposed to solve the reliability issues of emerging hybrid wired-wireless Network-on-Chip (WiNoC) architectures. Thus, providing a promising solution to the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing on future System-on-Chip (SoC) design. However, WiNoCs tradeoff optimized performance for cost by restricting the number of area and power hungry wireless nodes. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow wired routers in such emerging hyhbrid NoCs. The proposed router is able to redistribute traffic in the network to alleviate average packet latency at both low and high traffic conditions. As a second contribution the paper presents an experimental evaluation of a practically implemented surface wave communication fabric. By reducing the latency between the wired nodes and wireless nodes the proposed router can improve performance efficiency in terms of average packet delay by an average of 50% in WiNoCs.

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A wideband body-enabled millimeter-wave transceiver for wireless Network-on-Chip

Cited by 40 publications

References 17 publications

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Towards the practical design of performance-aware resilient wireless NoC architectures

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