A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors

DiTomaso, Dominic; Kodi, Avinash; Matolak, David W.; Kaya, Savaş; Laha, Soumyasanta; Rayess, William

doi:10.1109/tpds.2014.2383384

Cited by 75 publications

(40 citation statements)

References 26 publications

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“…Finally, it is worth noting that most of the other existing wired-wireless architectures in the literature [8], [9], [29], [36] share most of the design principles with MWNOC and HCWINOC: intertwining of both network planes, moderate number of antennas, and contention-free MAC. Therefore, their scalability trends will arguably be commensurate.…”

Section: Discussionmentioning

confidence: 99%

“…In most wired-wireless architectures, these channels are used to implement orthogonal links between distant cores [7], [8], [29], [36]. Even if implemented with multiple channels, ORTHONOC considers a single broadband link shared by all cores instead.…”

Section: Channelization and Rf Planningmentioning

confidence: 99%

“…Related works generally resort to contention-free mechanisms via multiplexing or variants of the popular token-passing protocol [7], [8], [36]. These methods do not scale well with the number of participating nodes due to the high cost of introducing new channels or the increase of the token round trip time [37].…”

Section: Medium Access Controlmentioning

confidence: 99%

“…In consonance with other works in the area [9], [30], [36], we choose a simple modulation leading to the use of a transceiver with affordable power and area overheads. Yu et al presented an On-Off Keying (OOK) implementation in the 30-90 GHz range capable of providing up to 48 Gb/s [30], enough for the evaluations carried out in this paper.…”

Section: Physical Layermentioning

confidence: 99%

“…Weissman et al describe a 65-nm design that provides 6 Gb/s with less than 0.1 mm 2 of area without the measurement pads [31]. In [36], the authors assume that a 40-nm transceiver operating at 32 Gb/s can have an area overhead in the range of 0.05-0.1 mm 2 . With these figures and empirical scaling projections [16], [32], we obtain conservative estimates at different technology nodes.…”

Section: Area Modelsmentioning

confidence: 99%

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OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

Abadal

Torrellas

Alarcón

et al. 2018

IEEE Trans. Parallel Distrib. Syst.

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Abstract-On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents ORTHONOC, a wired-wireless architecture that differs from existing proposals in that both network planes are decoupled and driven by traffic steering policies enforced at the network interfaces. With these and other design decisions, ORTHONOC seeks to emphasize the ordered broadcast advantage offered by the wireless technology. The performance and cost of ORTHONOC are first explored using synthetic traffic, showing substantial improvements with respect to other wired-wireless designs with a similar number of antennas. Then, the applicability of ORTHONOC in the multiprocessor scenario is demonstrated through the evaluation of a simple architecture that implements fast synchronization via ordered broadcast transmissions. Simulations reveal significant execution time speedups and communication energy savings for 64-threaded benchmarks, proving that the value of ORTHONOC goes beyond simply improving the performance of the on-chip interconnect.

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