A WLAN SoC for video applications including beamforming and maximum ratio combining

McFarland, W.; Choi, Woo-Young; Tehrani, A.M.; Gilbert, Judy B.; Kuskin, J.; Cho, J.; Smith, Jeff; Dua, P.; Breslin, D.; Ng, S.; Zhang, Xiaoru; Wang, Yi-Hsiu; Thomson, John; Unnikrishnan, M.; Mack, Mike; Mendis, S.R.; Subramanian, R.; Husted, P.; Hanley, Patrick; Zhang, Ning

doi:10.1109/isscc.2005.1494064

Cited by 8 publications

(1 citation statement)

References 2 publications

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“…Currently, the standard platform for sending video is 802.11g. However there exists a gap in bit-rate between narrow-band low-power transceivers, capable of sending data up to 2 Mbps, and WLAN transceivers capable of reaching 54 Mbps but consuming more than 500 mW [3].…”

Section: Introductionmentioning

confidence: 99%

Development of a versatile low-power 24 GHz phased array front-end in 90 nm CMOS technology

Tasselli

Wang

Ghamari

et al. 2012

10th IEEE International NEWCAS Conference

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Abstract-This paper deals with the development of a four-channel low-power Phased Array Front-End (PhA-FE) at 24 GHz, targeting both low-power radar sensors and battery powered transceiver applications. Typically, PhA-FEs are power hungry architectures due to multiple parallel RF channels in the FE and complex algorithms for beam steering or high bitrate demodulation in the digital part. In contrast, we target in this paper applications where both beam steering algorithms and data demodulation are relatively simple and hence achievable with low-power digital signal processing. More specifically, we report on four significant building blocks of the architecture, a Low Noise Amplifier (LNA), a Vector Modulator Phase Shifter (VMPS), a Quadrature Voltage Controlled Oscillator (QVCO) and an Analogue to Digital Converter (ADC) that have been designed the first three in 90nm and the last in 180nm CMOS technology. The LNA shows 24.4 dB gain, 3.4 dB NF and −24.4 dBm input P1dB. The single quadrant VMPS has more than 90• of phase control range and shows less than 0.7 dB of gain variation over phase shifting. The QVCO which consumes less than 32 mW, buffer included, has a tuning range of 8%. The 6bit 20 MS/s ADC consumes 1.8 mW.

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Section: Introductionmentioning

confidence: 99%