Accelerating Brain Circuit Simulations of Object Recognition with CELL Processors

Felch, Andrew; Nageswaran, Jayram Moorkanikara; Chandrashekar, Ashok; Furlong, Jeff; Dutt, Nikil; Granger, Richard; Nicolau, Alex; Veidenbaum, Alexander V.

doi:10.1109/iwia.2007.10

Cited by 3 publications

(4 citation statements)

References 15 publications

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“…Such findings may enable a range of applications in sensors, control systems, and robotics that are currently beyond the scope of standard approaches. The results reported herein and previously [6,7] demonstrate that alternate architectures can be constructed to provide large-scale parallelism, and may serve as platforms for research in currently recalcitrant computational tasks requiring real-time processing of real-world information, such as sensor processing, and perception.…”

Section: Resultsmentioning

confidence: 53%

“…Also, understanding and implementing brain-like systems in silicon is one of the grand challenges of the 21st century [2]. Recognizing this researchers are increasingly investigating brain mechanisms as models for novel algorithmic and architectural approaches [3][4][5][6][7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

“…We demonstrate its implementation in the IBM Cell processor [15,16] and in small clusters of these processors as in Sony Playstation 3 systems. 1 In this article we make two important contributions: first, we present the detailed computational model of the bottom-up engine in the BDV algorithm by extending our previous article [7]; second, we also show the various trade-offs in the implementation and performance prediction of this model on IBM CELL.…”

Section: Introductionmentioning

confidence: 99%

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Brain Derived Vision Algorithm on High Performance Architectures

Nageswaran

Felch

Chandrasekhar

et al. 2009

Int J Parallel Prog

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Even though computing systems have increased the number of transistors, the switching speed, and the number of processors, most programs exhibit limited speedup due to the serial dependencies of existing algorithms. Analysis of intrinsically parallel systems such as brain circuitry have led to the identification of novel architecture designs, and also new algorithms than can exploit the features of modern multiprocessor systems. In this article we describe the details of a brain derived vision (BDV) algorithm that is derived from the anatomical structure, and physiological operating principles of thalamo-cortical brain circuits. We show that many characteristics of the BDV algorithm lend themselves to implementation on IBM CELL architecture, and yield impressive speedups that equal or exceed the performance of specialized solutions such as FPGAs. Mapping this algorithm to the IBM CELL is non-trivial, and we suggest various approaches to deal with parallelism, task granularity, communication, and memory locality. We also show that a cluster of three PS3s (or more) containing IBM CELL processors provides a promising platform for brain derived algorithms, exhibiting speedup of more than 140× over a desktop PC implementation, and thus enabling real-time object recognition for robotic systems.

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Section: Resultsmentioning

confidence: 53%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Brain Derived Vision Algorithm on High Performance Architectures

Nageswaran

Felch

Chandrasekhar

et al. 2009

Int J Parallel Prog

Self Cite

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show abstract

“…A prototype of the above vision algorithm was tested on a class of difficult data ( Figure 4.16 ) and performance was shown to closely match the current best system at the task (Carmichael, 2003 ;Felch et al ., 2007 ); however, these tests took several days to compute. Research is being conducted in order to develop new computer hardware architectures that utilize the intrinsic parallelism of the algorithm to greatly improve performance while satisfying the low power requirements of mobile robots.…”

Section: 32mentioning

confidence: 90%