Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation

Hsieh, Kevin; Khan, Samira; Vijaykumar, Nandita; Chang, Ki-Ho; Boroumand, Amirali; Ghose, Saugata; Mutlu, Onur

doi:10.1109/iccd.2016.7753257

Cited by 151 publications

(140 citation statements)

References 70 publications

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“…Hybrid Memory Cube (HMC) is developed by a number of different contributing companies [12,44]. Like HBM, HMC also enables a logic layer underneath the DRAM layers that can perform computation [6,42,43]. HMC is already integrated in the SPARC64 XIfx chip [101].…”

Section: D-stacked Memorymentioning

confidence: 99%

“…In contrast, processing-in-memory (PIM)-enabled devices such as 3D-stacked memory can perform simple arithmetic operations very close to where the data resides, with high bandwidth and low latency. With carefully designed algorithms for PIM, application performance can often be greatly improved (e.g., as shown in [6,42,43,92]) because the relatively narrow and long-latency bus between the CPU cores and memory no longer impedes the speed of computation on the data.…”

Section: Introductionmentioning

confidence: 99%

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GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies

et al. 2018

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BackgroundSeed location filtering is critical in DNA read mapping, a process where billions of DNA fragments (reads) sampled from a donor are mapped onto a reference genome to identify genomic variants of the donor. State-of-the-art read mappers 1) quickly generate possible mapping locations for seeds (i.e., smaller segments) within each read, 2) extract reference sequences at each of the mapping locations, and 3) check similarity between each read and its associated reference sequences with a computationally-expensive algorithm (i.e., sequence alignment) to determine the origin of the read. A seed location filter comes into play before alignment, discarding seed locations that alignment would deem a poor match. The ideal seed location filter would discard all poor match locations prior to alignment such that there is no wasted computation on unnecessary alignments.ResultsWe propose a novel seed location filtering algorithm, GRIM-Filter, optimized to exploit 3D-stacked memory systems that integrate computation within a logic layer stacked under memory layers, to perform processing-in-memory (PIM). GRIM-Filter quickly filters seed locations by 1) introducing a new representation of coarse-grained segments of the reference genome, and 2) using massively-parallel in-memory operations to identify read presence within each coarse-grained segment. Our evaluations show that for a sequence alignment error tolerance of 0.05, GRIM-Filter 1) reduces the false negative rate of filtering by 5.59x–6.41x, and 2) provides an end-to-end read mapper speedup of 1.81x–3.65x, compared to a state-of-the-art read mapper employing the best previous seed location filtering algorithm.ConclusionGRIM-Filter exploits 3D-stacked memory, which enables the efficient use of processing-in-memory, to overcome the memory bandwidth bottleneck in seed location filtering. We show that GRIM-Filter significantly improves the performance of a state-of-the-art read mapper. GRIM-Filter is a universal seed location filter that can be applied to any read mapper. We hope that our results provide inspiration for new works to design other bioinformatics algorithms that take advantage of emerging technologies and new processing paradigms, such as processing-in-memory using 3D-stacked memory devices.

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Section: D-stacked Memorymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies

et al. 2018

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“…However, practical concerns regarding the successful integration of DRAM and processing units into the same chip have hindered the advancement of such NMC systems for many years. Recently, the advent of 3D stacking memories that employ massive through-silicon-vias (TSVs) provides larger bandwidth while allowing the integration of logic and memory into a stacked chip (e.g., [13,15,16,20,30]).…”

Section: Computing In Memorymentioning

confidence: 99%

“…Recent works (e.g., [4,15,16,17,18,19,20,21,22,23,24,25]) in both CMOS Static Random Access Memory (SRAM) and emerging non-volatile memories (NVMs) have demonstrated various CiM designs at different levels of memory hierarchy. The designs allow computation to occur exactly where data resides, thereby reducing energy and performance overheads associated with data movement.…”

Section: Introductionmentioning

confidence: 99%

Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures

Gao

Reis

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Computing-in-Memory (CiM) architectures aim to reduce costly data transfers by performing arithmetic and logic operations in memory and hence relieve the pressure due to the memory wall. However, determining whether a given workload can really benefit from CiM, which memory hierarchy and what device technology should be adopted by a CiM architecture requires in-depth study that is not only time consuming but also demands significant expertise in architectures and compilers. This paper presents an energy evaluation framework, Eva-CiM, for systems based on CiM architectures. Eva-CiM encompasses a multi-level (from device to architecture) comprehensive tool chain by leveraging existing modeling and simulation tools such as GEM5 [1], McPAT [2] and DESTINY [3]. To support high-confidence prediction, rapid design space exploration and ease of use, Eva-CiM introduces several novel modeling/analysis approaches including models for capturing memory access and dependencyaware ISA traces, and for quantifying interactions between the host CPU and CiM modules. Eva-CiM can readily produce energy estimates of the entire system for a given program, a processor architecture, and the CiM array and technology specifications. Eva-CiM is validated by comparing with DESTINY [3] and [4], and enables findings including practical contributions from CiM-supported accesses, CiM-sensitive benchmarking as well as the pros and cons of increased memory size for CiM. Eva-CiM also enables exploration over different configurations and device technologies, showing 1.3-6.0× energy improvement for SRAM and 2.0-7.9× for FeFET-RAM, respectively.

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“…Thus, during the last decade, scientists have experimented with the integration of novel algorithms that perform dynamic, in-memory data rearrangements of irregular structures [22,23]. The aim is to overcome (or partially hide) some of the aforementioned limitations.…”

Section: Introductionmentioning

confidence: 99%

Exploring the Vision Processing Unit as Co-Processor for Inference

Rivas-Gomez

Peña²,

Moloney

et al. 2018

2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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The success of the exascale supercomputer is largely debated to remain dependent on novel breakthroughs in technology that effectively reduce the power consumption and thermal dissipation requirements. In this work, we consider the integration of co-processors in high-performance computing (HPC) to enable low-power, seamless computation offloading of certain operations. In particular, we explore the so-called Vision Processing Unit (VPU), a highly-parallel vector processor with a power envelope of less than 1W.We evaluate this chip during inference using a pre-trained GoogLeNet convolutional network model and a large image dataset from the ImageNet ILSVRC challenge. Preliminary results indicate that a multi-VPU configuration provides similar performance compared to reference CPU and GPU implementations, while reducing the thermal-design power (TDP) up to 8× in comparison.

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Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation

Cited by 151 publications

References 70 publications

GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies

GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies

Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures

Exploring the Vision Processing Unit as Co-Processor for Inference

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