Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs

Zhang, Kai; Chen, Shuming; Liu, Sheng; Wang, Yaohua

doi:10.1109/asicon.2011.6157297

Cited by 5 publications

(5 citation statements)

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“…Several previous works have fused memory-access and shuffle instructions functionally to accelerate FFTlike algorithms. Reference [7] proposed VHALFUP and VHALFDN instructions that can reduce some of the shuffle operations in the mapping of FFT algorithms, but only the time-domain radix-2 FFT algorithm is considered, and an additional MOV operation is required to store the intermediate results of the two instructions. The VEXC instruction proposed in [8] eliminates the extra MOV operation in [7].…”

Section: Related Workmentioning

confidence: 99%

“…Reference [7] proposed VHALFUP and VHALFDN instructions that can reduce some of the shuffle operations in the mapping of FFT algorithms, but only the time-domain radix-2 FFT algorithm is considered, and an additional MOV operation is required to store the intermediate results of the two instructions. The VEXC instruction proposed in [8] eliminates the extra MOV operation in [7]. However, it adds an extra register write port, and considers only the time-domain radix-2 FFT algorithm, thus has no acceleration effect on other types of FFT algorithms.…”

Section: Related Workmentioning

confidence: 99%

“…In order to evaluate various approaches to implement the FFT algorithm, we add the VHALFUP and VHALFDN instructions in FT-Matrix-Sim regarding [7] and the VEXC from [8]. In addition, the FT-Matrix includes the shuffle unit and the vector memory-access shuffle fused instructions proposed above.…”

Section: Performance Optimization 1) Experimental Setupmentioning

confidence: 99%

“…2) Performance improvement of common FFT algorithms Table 3 gives the normalized speedup ratio for five implementations of the FFT computation in radix-2/4 and DIF/DIT for 1024 and 4096 points single/double floating complex number. The VHALFUP/DN method proposed in reference [7] and the VEXC in [8] are only applicable to the radix-2 FFT algorithm but not to the radix-4. The NIP proposed in this paper and the further NIP_VLSSF can achieve performance improvement in both radix-2 and radix-4 FFT algorithms.…”

Section: Vector Memory Access Shuffle Load Instructionmentioning

confidence: 99%

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Vector Memory-Access Shuffle Fused Instructions for FFT-Like Algorithms

Liu,

Yuan,

Guo

et al. 2023

Chinese J. Elect.

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The shuffle operations are the bottleneck when mapping the FFT-like algorithms to the vector single instruction multiple data (SIMD) architectures. We propose six (three pairs) innovative vector memoryaccess shuffle fused instructions, which have been proved mathematically. Combined with the proposed modified binary-exchange method, the innovative instructions can efficiently address the bottleneck problem for decimationin-frequency or decimation-in-time (DIF/DIT) radix-2/4 FFT-like algorithms, reach a performance improvement by 17.9%-111.2% and reduce the code size by 5.4%-39.8%. In addition, the proposed instructions fit some hybridradix FFTs and are suitable for the terms of the initial or result data placement for general algorithms. The software and hardware costs of the proposed instructions are moderate.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Performance Optimization 1) Experimental Setupmentioning

confidence: 99%

Section: Vector Memory Access Shuffle Load Instructionmentioning

confidence: 99%

See 2 more Smart Citations

Vector Memory-Access Shuffle Fused Instructions for FFT-Like Algorithms

Liu,

Yuan,

Guo

et al. 2023

Chinese J. Elect.

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“…As for implementing Fast Fourier Transforms (FFTs) on Single Instrustion Multiple Data (SIMD) instruction digital signal processing (DSP) processors [6,14,17,21], to the best of our knowledge, no such work is performed on BP polar code decoders. Therefore, our work provides not only a novel hardware solution, but also a novel approach for the implementation of BP polar code decoders on DSPs, which allow the definition of application specific SIMD instructions for Polar code decoding, like in the Cadence Tenscilica ConnX family DSPs.…”

Section: Related Workmentioning

confidence: 99%

Conflict-Free Vectorized In-order In-place Radix-r Belief Propagation Polar Code Decoder Algorithm

Brink

Bekooij

2020

Proceedings of the 2020 8th International Conference on Communications and Broadband Networking

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A vectorized belief propagation polar code decoder is desirable because of the potentially high throughput and the ability of integration in processors that perform vectorized processing and access wide memory words. However, current state-of-the-art belief propagation polar code decoder algorithms do not perform vector processing and store intermediate results in non consecutive memory locations. Also the current state-of-the-art belief propagation polar code decoders require separate memories to store left and right bound intermediate results.In this paper we propose a vectorized in-order in-place belief propagation polar code decoder algorithm where all stages access vectorized data from memory. This results in a high throughput because vectors of elements can be fetched from and stored in memory in each clock cycle. Our algorithm also accommodates for per stage in-place computations which halves the required internal memory. Furthermore, the algorithm has a regular memory addresses access pattern. Conflict free vectorized memory access is achieved by making use of transpose operations on small groups of intermediate results. The use of the transpose operations also results in that both input and output results are placed on subsequent locations in memory.

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