Accelerator-Rich Architectures

Cong, Jason; Ghodrat, Mohammad Ali; Gill, Michael; Grigorian, Beayna; Gururaj, Karthik; Reinman, Glenn

doi:10.1145/2593069.2596667

Cited by 73 publications

(13 citation statements)

References 17 publications

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“…However, low power and energy consumptions are other important features of FPGAs that have recently grabbed the researchers' attention to provide energy efficient yet fast platforms. Accelerator rich platforms [1] are among the state-of-the-art ideas to improve the energy efficiency by offloading computation from CPU cores to accelerators and increase the utilisation of resources in the future dark silicon era [2]. FPGAs are among the technologies used in these platforms [3].…”

Section: Introductionmentioning

confidence: 99%

Energy optimization of FPGA-based stream-oriented computing with power gating

Hosseinabady

Nunez-Yanez

2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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Section: Introductionmentioning

confidence: 99%

Energy optimization of FPGA-based stream-oriented computing with power gating

Hosseinabady

Nunez-Yanez

2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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“…It uses a 720p high-definition H.264 encoder as the application driver, and a four-core CMP system using the Tensilica extensible RISC cores [119] as the baseline processor configuration. is leads to accelerator-rich architectures, which have received a growing interest in recent years [26,28,89]. Adding 16-wide SIMD execution units to the baseline cores improves the performance by 10X and energy efficiency by 7X.…”

Section: Introductionmentioning

confidence: 99%

“…Examples include the use of fine-grain field-programmable gate arrays (FPGAs), coarse-grain reconfigurable arrays [61,62,91,94,118], or dynamically composable accelerator building blocks [26,27]. Examples include the use of fine-grain field-programmable gate arrays (FPGAs), coarse-grain reconfigurable arrays [61,62,91,94,118], or dynamically composable accelerator building blocks [26,27].…”

Section: Introductionmentioning

confidence: 99%

“…As a result, conventional cores cannot be as efficient at performing a particular task as a hardware structure that is more specialized to that purpose [26]. For example, out-of-order processing benefits considerably from short latency instructions, as long latency instructions can cause pipeline stalls.…”

Section: Introductionmentioning

confidence: 99%

“…For example, out-of-order processing benefits considerably from short latency instructions, as long latency instructions can cause pipeline stalls. Taken from [26]. As a result, conventional cores cannot be as efficient at performing a particular task as a hardware structure that is more specialized to that purpose [26].…”

Section: Introductionmentioning

confidence: 99%

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Synthesis Lectures on Computer Architecture publishes 50-to 100-page publications on topics pertaining to the science and art of designing, analyzing, selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals. e scope will largely follow the purview of premier computer architecture conferences, such as ISCA, HPCA, MICRO, and ASPLOS. ABSTRACTSince the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. e large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development on customizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems.

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Reconfigurable Computing

Boland

Chung-Kuan

Kahng

et al. 2017

Wiley Encyclopedia of Electrical and Electronics Engineering

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Reconfigurable computing is the application of adaptable fabrics to address computational problems, often taking advantage of the flexibility of field‐programmable gate arrays (FPGAs) to produce problem‐specific solutions. It has been successfully applied to fields as diverse as machine learning, digital signal processing, cryptography, bioinformatics, logic emulation, CAD tool acceleration, scientific computing, and rapid prototyping.In this article, intended for the nonspecialist, we describe some of the basic concepts, tools, and architectures associated with reconfigurable computing.

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Accelerator-Rich Architectures

Cited by 73 publications

References 17 publications

Energy optimization of FPGA-based stream-oriented computing with power gating

Energy optimization of FPGA-based stream-oriented computing with power gating

Customizable Computing

Reconfigurable Computing

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