Acceptor defects in polycrystalline Ge layers evaluated using linear regression analysis

Abstract

Polycrystalline Ge thin films have recently attracted renewed attention as a material for various electronic and optical devices. However, the difficulty in the Fermi level control of polycrystalline Ge films owing to their high density of defect-induced acceptors has limited their application in the aforementioned devices. Here, we experimentally estimated the origin of acceptor defects by significantly modulating the crystallinity and electrical properties of polycrystalline Ge layers and investigating their correlation. Our proposed linear regression analysis method, which is based on deriving the acceptor levels and their densities from the temperature dependence of the hole concentration, revealed the presence of two different acceptor levels. A systematic analysis of the effects of grain size and post annealing on the hole concentration suggests that deep acceptor levels (53–103 meV) could be attributed to dangling bonds located at grain boundaries, whereas shallow acceptor levels (< 15 meV) could be attributed to vacancies in grains. Thus, this study proposed a machine learning-based simulation method that can be widely applied in the analysis of physical properties, and can provide insights into the understanding and control of acceptor defects in polycrystalline Ge thin films.

n-Type Polycrystalline Germanium Layers Formed by Impurity-Doped Solid-Phase Growth

“…This behavior is interpreted as passivation of grain boundary traps, as in the p-type Ge layer. 36 In contrast, PA increased the Q t and E B values of the Sb-doped sample, possibly because of the segregation of Sb, which has a high diffusion coefficient at the grain boundaries. 37,38 The E B values together with the grain size in Figure 3 account for the trend of μ n in Figures 5a and 5b.…”

“…Fortunately, the crystallization temperature of Ge is lower than that of Si, and many low-temperature synthesis methods have been proposed, including solid-phase crystallization (SPC), − laser annealing, − chemical vapor deposition, , lamp annealing, , plasma irradiation, seed layer technique, and metal-induced crystallization. − Although these methods produce polycrystalline Ge layers containing grain boundaries, large grain size and grain boundary control enable quasi-single-crystal channels in transistors. ,,, Most of these polycrystalline Ge films are p-type, whereas reports on n-type Ge have been limited. This is because Ge tends to be p-type owing to the high density (10 17 –10 18 cm –3 ) of acceptor defects , and low n-type dopant activation rates. , Therefore, the synthesis of high-quality polycrystalline Ge layers is essential for obtaining n-type Ge layers in low-temperature processes.…”

“…20,21,28,32 Most of these polycrystalline Ge films are p-type, whereas reports on n-type Ge have been limited. This is because Ge tends to be p-type owing to the high density (10 17 −10 18 cm −3 ) of acceptor defects 35,36 and low n-type dopant activation rates. 37,38 Therefore, the synthesis of high-quality polycrystalline Ge layers is essential for obtaining n-type Ge layers in lowtemperature processes.…”

Interfacial Nucleation Control in Amorphous GeSn Thin Films Using Bilayer Structure

“…As a result of Hall measurements, all samples showed p-type conduction owing to acceptor defects. Since acceptor defects in poly-Ge exist not only within grains but also at grain boundaries, p was lower for larger grain sizes. Because carrier mobility is affected by carrier scattering by grain boundaries, , μ p was dependent on grain size, reaching a maximum at T d = 125 °C.…”

“…Among the aforementioned methods, SPC has made remarkable progress in recent years. Densification and elemental doping in amorphous Ge (a-Ge) precursors have dramatically increased the grain size of the poly-Ge layers after SPC. − Reflecting the reduced grain boundary scattering, high Hall carrier mobilities (electron: 380 cm 2 V –1 s –1 , hole: 690 cm 2 V –1 s –1 ) have been achieved. , However, thicker (>100 nm) Ge films were essential for achieving such high carrier mobilities because thinner Ge films exhibit poorer crystallinity such as smaller grain size. − Furthermore, acceptor defects in Ge complicate the low carrier concentration of poly-Ge layers. , These features hamper TFT operation because the off-current reduction requires full depletion, which can be achieved by a thin Ge film and low carrier concentration . We have achieved p-channel accumulation-mode TFTs using 50 nm thick GeSn .…”