Active Mode Subclock Power Gating

Mistry, Jatin N.; Myers, James; Al-Hashimi, Bashir M.; Flynn, David; Biggs, John; Merrett, Geoff V.

doi:10.1109/tvlsi.2013.2280886

Cited by 15 publications

(2 citation statements)

References 21 publications

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“…MTCMOS technique as one of the most well-known techniques (Figure 1(a)), isolates network from power supply and ground by using high threshold voltage switch transistors [11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits

Alimoradi¹,

Rostami²,

Karami³

2018

IJCA

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In this paper, a novel approach at circuit level named LSP is proposed by combination of LECTOR, Stack and Pass transistors techniques to decrease leakage power dissipation during active and standby mode. As a result, pass transistors are utilized to maintain logic state of network in the standby mode. Proposed technique simulation has been performed using HSPICE software in 32 nanometer technology with supply voltage 0.6V. According to achieved results by NAND gate and full adder circuits, sub-threshold current is decreased by 80% in compared to base case, 70% to LECTOR and 20% to Sleepy Keeper.

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“…MTCMOS technique as one of the most well-known techniques (Figure 1(a)), isolates network from power supply and ground by using high threshold voltage switch transistors [11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits

Alimoradi¹,

Rostami²,

Karami³

2018

IJCA

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“…It can effectively reduce the static power consumption 10-times more than the other design techniques such as clock gating, and dynamic voltage=frequency scaling. [20][21][22][23] However, the PG technique cannot reach its potential for power reduction of the associative processor based on large volatile memory. It is very difficult to shut off any part of the processor during operation.…”

Section: Introductionmentioning

confidence: 99%

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

Honjo

Ikeda

et al. 2016

Jpn. J. Appl. Phys.

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A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

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A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architecture

Arumugam¹,

Viswanaathan²

2016

Circuit Theory & Apps

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SummaryClock distribution networks consume a significant amount of the whole chip power budget. Therefore, reduction in the power consumption of the clock networks is a significant objective in high‐performance Integrated Circuit (IC) designs. This paper presents a novel Particle Distance Weighted Clustering (PDWC)‐Unity Clustering Optimization (UCO) algorithm for the placement of clock buffers in the Field Programmable Gate Array (FPGA) architecture. A novel PDWC algorithm is applied for clustering the logical components based on the minimum distance between components. A UCO algorithm is developed to determine the location for the placement of the buffers. This clustering technique reduces the delay rate of the architecture because of the minimum number of logical components. The overall area and power consumption of the FPGA architecture are reduced because of the placement of the buffers and latches. Our proposed PDWC‐UCO algorithm achieves lower delay, power consumption, wire length, latency and skew than the existing Flip‐Flop (FF) merging and register clustering algorithms. Copyright © 2016 John Wiley & Sons, Ltd.

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Active Mode Subclock Power Gating

Cited by 15 publications

References 21 publications

Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits

Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architecture

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