Adiabatic 4-bit adders: comparison of performance and robustness against technology parameter variations

Amirante, E.; Bargagli-Stoffi, A.; Fischer, Jürgen; Iannaccone, Giuseppe; Schmitt‐Landsiedel, D.

doi:10.1109/mwscas.2002.1187122

Cited by 9 publications

(3 citation statements)

References 11 publications

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“…Among the MOSFET-only logic families, PFAL shows the best properties in the high frequency range (Amirante et al, 2001(Amirante et al, , 2002. Figure 1 shows the general schematic of a PFAL gate.…”

Section: Adiabatic Logic Familiesmentioning

confidence: 99%

Improving the positive feedback adiabatic logic familiy

et al. 2005

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Abstract. Positive Feedback Adiabatic Logic (PFAL) shows the lowest energy dissipation among adiabatic logic families based on cross-coupled transistors, due to the reduction of both adiabatic and non-adiabatic losses. The dissipation primarily depends on the resistance of the charging path, which consists of a single p-channel MOSFET during the recovery phase. In this paper, a new logic family called Improved PFAL (IPFAL) is proposed, where all n-and pchannel devices are swapped so that the charge can be recovered through an n-channel MOSFET. This allows to decrease the resistance of the charging path up to a factor of 2, and it enables a significant reduction of the energy dissipation. Simulations based on a 0.13µm CMOS process confirm the improvements in terms of power consumption over a large frequency range. However, the same simple design rule, which enables in PFAL an additional reduction of the dissipation by optimal transistor sizing, does not apply to IPFAL. Therefore, the influence of several sources of dissipation for a generic IPFAL gate is illustrated and discussed, in order to lower the power consumption and achieve better performance.

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Section: Adiabatic Logic Familiesmentioning

confidence: 99%

Improving the positive feedback adiabatic logic familiy

et al. 2005

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“…Former work [9] has shown their good energy saving factor over static CMOS. In figure 1 the schematics of ECRL and PFAL are shown.…”

Section: Considered Logic Familiesmentioning

confidence: 99%

Scaling trends in adiabatic logic

Fischer

Teichmann

Schmitt‐Landsiedel

2005

Proceedings of the 2nd Conference on Computing Frontiers

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Adiabatic circuits which are able to dissipate less energy than the fundamental limit of static CMOS are promising candidates for low-power circuits in the frequency range in which signals are digitally processed. This paper shows the main sources of the energy dissipation in adiabatic circuits. It will be presented that with state-of-the-art transistors the distinction between quasi-and fully adiabatic circuits has become obsolete. With the shrinking of the transistor dimensions, new leakage mechanisms like gate leakage occur. As the adiabatic circuits work with an oscillating power supply, leakage currents flow only a part of the period. Without any further effort adiabatic circuits save about 30% of energy dissipation caused by leakage. As in static CMOS, adiabatic circuits benefit from voltage scaling. The Efficient Charge Recovery Logic scales linearly down to supply voltages near the threshold voltage. Simulations with a sinusoidal power supply showed no significant difference to a trapezoidal supply at most frequencies. For overall dissipation accounting also for generator efficiency and attenuation on the wiring, the sinusoidal supply voltage should be preferred.

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“…It could save up to 30% of energy compared to static CMOS at 100 MHz. E. Amirante [5] implemented 4-bit adiabatic adder using ECRL, 2N-2N2P and PFAL families. These three were compared in terms of energy consumption, area occupation and frequency range.…”

Section: Introductionmentioning

confidence: 99%

Power dissipation reduction using adiabatic logic techniques for CMOS inverter circuit

Pindoo

Singhy

Singh

et al. 2015

2015 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT)

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Power dissipation in circuits and systems is the critical factor for most of the researchers and industries. Many power dissipation techniques have been proposed but most of these techniques have some tradeoffs. Adiabatic logic technique in contrary to that of a conventional CMOS technique shows promising results. A variable supply voltage is provided instead of a constant supply required for CMOS logic. In this paper, an unconventional approach for reducing the power dissipation is reviews and implemented. Various techniques used for implementing adiabatic logic circuits are also discussed in this paper. The adiabatic CMOS and the conventional CMOS techniques are compared with respect to their power dissipation parameter. The simulation results obtained verifies that the circuits implemented using adiabatic logic approach dissipate lesser power compared to that of conventional static CMOS approach.

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Adiabatic 4-bit adders: comparison of performance and robustness against technology parameter variations

Cited by 9 publications

References 11 publications

Improving the positive feedback adiabatic logic familiy

Improving the positive feedback adiabatic logic familiy

Scaling trends in adiabatic logic

Power dissipation reduction using adiabatic logic techniques for CMOS inverter circuit

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