2015 39th National Systems Conference (NSC) 2015
DOI: 10.1109/natsys.2015.7489090
|View full text |Cite
|
Sign up to set email alerts
|

Adiabatic technique for fat tree decoder to be used in flash ADCs

Abstract: Today power dissipation is the most critical problem in Low Power circuits in VLSI design . Adiabatic technique is a technique to reduce power dissipation in digital circuits in which energy stored in a capacitor can be recycled rather than dissipated as heat. In this paper the Fat tree decoder incorporating PFAL i.e. Positive Feedback Adiabatic Logic technique has been simulated using SPICE simulation tool and its power dissipation has been calculated . In this technique , the energy is recovered during recov… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Year Published

2022
2022
2022
2022

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
references
References 11 publications
0
0
0
Order By: Relevance