Adopting multi-valued logic for reduced pin-count testing

Abstract

The reduced pin-count test (RPCT) has been proposed for testing cost reduction in various scenarios like scan, test compression and multi-site test. In this paper, we propose a new RPCT technique in which several digital signals are combined into a single multi-valued logic (MVL) signal. Mixed-signal components, digital-to-analog and analogto-digital converters, are used to compress the tester channels and then to expand the test at the circuit under test. The method allows greater bandwidth efficiency than the existing SerDes alternative. However, the MVL signal can be sensitive to noise and nonlinearity errors. To ensure the reliability of test application, we provide an error control scheme. The paper gives theoretical analysis as well as experimental evidence.

Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing

“…Because the performance of DAC and ADC may fluctuate in different environmental conditions, calibration should be done prior to test data transfer. We have demonstrated the effectiveness of the calibration scheme [14]. But sometime the performance of ADC (such as non-monotonicity or missing code) a possible fix.…”

“…Based on recent work [12], [13], [14], we combine MVL test channels with RPCT interface shown in Figure 2 (c). Here we assume that the ATE channel is capable of generating 200MHz signal.…”

“…In the past [12], [13], [14], we have discussed possible reliability issues and solutions associated with an MVL test channel. We identified two error sources: data converter nonlinearities and noise.…”

“…It is reasonable to assume [14] that DACs integrated in ATE have good performance and can be controlled by users. But the ADC in DUT is as fabricated and may not be perfect.…”

“…The primary cause of this is the limit test channel data rate clamping the DUT scan speed. We recently proposed [12], [13], [14] the idea of using multi-valued logic (MVL) as test data format which greatly increases the data rate of test channels. In this work, we integrate such an MVL scheme in test compression compatible RPCT technology to enable ATE support for higher scan speed in RPCT or to further reduce the number of test pins.…”