Advances in high-k dielectric gate materials for future ULSI devices

Abstract

Overview Microelectronic ProcessingThis article discusses recent developments in high dielectric constant gate insulator materials for future ultra-large-scale integration devices below 100 nm. Since conventional gate oxide poses problems as device features are scaled down, it becomes necessary to develop new gate dielectric materials with properties similar to SiO 2 and compatible with current complementary metal-oxide semiconductor technology. As the thickness of silicon dioxide approaches less than 1.5 nm, the leakage current becomes higher than 1 A/cm 2 and tunnel current increases significantly. Therefore, materials are needed to provide excellent electrical characteristics such as dielectric constant higher than 30, interface-state-density less than 1 ¥ 10 11 / cm 2 -eV, tunneling current less than 10 mA/ cm 2 , and negligible hysteresis. Many high dielectric constant materials have been reported that could potentially replace SiO 2 . These include SiO x N , and silicates of hafnium and zirconium. These materials exhibit the desired high dielectric constants for applications as gate dielectrics in sub-100 nm silicon technology. However, detailed studies need to be performed to evaluate the compatibility of these materials with the rest of the silicon integrated-circuit manufacturing processes.

Thermal oxidation and nitridation of sputtered Zr thin film on Si via N2O gas

“…Hence, reaction between Zr and O may be uncompleted and sub-stoichiometric Zr-O is formed at the interfacial layer. Simultaneously, owing to the out-diffusion of Si atom and reaction with the sub-stoichiometric Zr-O, Zr-Si-O compound may be formed [43,[68][69][70][71]:…”

MOCVD and ALD of CeO2 Thin Films using a Novel Monomeric CeIV Alkoxide Precursor

“…[5] CeO 2 has also been added to HfO 2 in order to stabilise the high-k cubic and tetragonal phases for potential applications in nextgeneration, sub-32 nm node CMOS devices. [6] Metal-organic (MO) CVD and atomic layer deposition (ALD) are the most attractive techniques for the deposition of CeO 2 for microelectronics applications.…”

Mismatch of dielectric constants at the interface of nanometer metal-oxide-semiconductor devices with high-K gate dielectric impacts on the inversion charge density

“…Researches related to high-K dielectrics are increasing rapidly because of their potential for substituting silicon dioxide in microelectronic devices [1][2][3][4][5][6][7][8]. Among the high-K alternatives, hafnium oxide is very promising.…”