AetEC: Adaptive error-tolerant Erasure Coding Scheme Within SSDs

Zhan, Tianqi; Wang, Xianpeng; Feng, Dan; Tong, Wei

doi:10.1109/iccd50377.2020.00041

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…Por ejemplo, [25] define cuatro niveles de error con el fin de corregir fallos múltiples adyacentes. En el caso de [26], y utilizando códigos Reed-Solomon, se definen también diferentes niveles de protección. Otro ejemplo similar se puede ver en [27], en el que también se definen varios niveles de error, y a cada nivel se aplica un ECC distinto.…”

Section: Trabajos Previos De Tolerancia a Fallos Adaptativaunclassified

“…Esta configuración está inspirada en trabajos como los presentados en [25][26][27] [28], donde los autores dividen la memoria en bloques y, en función de un mapa de bloques de fiabilidad calculado previamente, asignan un ECC diferente a cada bloque. Por ejemplo, en [26] y [27] se cambia de ECC en función de la tasa de errores, mientras que en [28] cada ECC tiene un número diferente de bits de código, dependiendo de si el bloque necesita una mayor o menor protección contra errores. En nuestro ejemplo, todos los ECC tienen el mismo número de bits redundantes.…”

Section: B Modelos Vhdl Utilizadosunclassified

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A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

Gracia-Morán,

Saiz-Adalid,

Baraza-Calvo

et al. 2024

IEEE Latin Am. Trans.

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Actual memory systems provide large storage capacity thanks to the integration scale level achieved in CMOS technology. This increment in storage capacity comes with an augment on their fault rate. In this way, the probability of experiencing Single or Multiple Cell Upsets has risen. Error Correction Codes (ECC) are a fault-tolerant mechanism broadly employed to protect memory systems. Usually, an ECC-based fault tolerance mechanism is designed with fixed correction and detection capabilities. However, in some contexts, current memory systems can suffer a variable fault rate during their operation. Thus, it seems very interesting that this fault-tolerant mechanism would be able to adapt to these variable fault conditions. This work proposes an Adaptive Fault-Tolerant mechanism based on ECC. This mechanism can adapt to different fault conditions, being able to correct and/or detect single and multiple bits in error. The Adaptive Fault-Tolerant mechanism proposed uses a unique encoder and various decoders. Therefore, there is no need to re-encode the data to change the error coverage since the unique encoder and the equal redundancy are the same regardless of the fault tolerance required. In addition, we have studied the area, delay, and power consumption overheads produced by the inclusion of the redundant bits, the encoder, and the decoders of the ECC in a computer system.

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Section: Trabajos Previos De Tolerancia a Fallos Adaptativaunclassified

Section: B Modelos Vhdl Utilizadosunclassified

A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

Gracia-Morán,

Saiz-Adalid,

Baraza-Calvo

et al. 2024

IEEE Latin Am. Trans.

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ZoneLife: How to Utilize Data Lifetime Semantics to Make SSDs Smarter

Chen

Chang

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Flash-oriented Coded Storage: Research Status and Future Directions

Li,

Zhang,

Wang

2024

ACM Trans. Storage

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Flash-based solid-state drives (SSDs) have been widely adopted in various storage systems, manifesting better performance than their forerunner HDDs. However, the characteristics of flash media post some drawbacks when deploying SSD-based storage systems. First, flash media have limited program/erase cycles, making them vulnerable to media failures. Second, SSD foreground I/Os can suffer from inconsistent performance due to interference from background operations like garbage collection (GC). The major solution to the above problems is to introduce data redundancy. Redundant data can not only detect raw bit errors and recover lost data but also enable I/O scheduling to sidestep SSDs that are under performance degradation. Compared with multi-replica, data coding is a more space-efficient way to provide redundancy. However, it is more challenging to simultaneously achieve low access latency, consistent performance and fast recovery. This paper examines the design of coded storage in existing storage systems, with a focus on flash storage systems, and how they address these challenges. The coded storage techniques are categorized into in-device coding, cross-device coding, and cross-machine coding. They are designed for different scenarios and purposes, but share some design rationales in common. For each type of coded storage, we begin by presenting the theoretical bases, followed by an overview of how existing studies address the performance and endurance issues of coded storage from a systemic perspective. Finally, we review the history of coded storage, list several key insights from existing works, and speculate some promising directions for flash-oriented coded storage systems.

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AetEC: Adaptive error-tolerant Erasure Coding Scheme Within SSDs

Cited by 3 publications

References 11 publications

A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

ZoneLife: How to Utilize Data Lifetime Semantics to Make SSDs Smarter

Flash-oriented Coded Storage: Research Status and Future Directions

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