Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications

Hsieh, Jui-Hung; Chang, Tian-Sheuan

doi:10.1109/tvlsi.2011.2178439

Cited by 8 publications

(8 citation statements)

References 24 publications

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“…The simulation conditions are CIF-size test sequences with the main profile, simple R-D optimization, one reference frame, full-search algorithm in ME, IPPP sequences, 30 frames/s, CABAC entropy coder. Table I presents the performance comparison between the proposed scheme and the fix-SR scheme in constant data-bandwidth (CDB) patterns, as well as the proposed scheme and the simple-SR scheme (defined in JM as "adaptive motion search range") in variable data-bandwidth (VDB) patterns; in this comparison, the CDB patterns [9] mean that the system BW during ME operations is constant and fixed, whereas, the VDB patterns [9] denote that the operating system prefers different low power modes. The performance of the proposed method was measured using the PSNR difference of luma in dB ( PSNR), the percentage change in bit-rate ( Rate), and the decrease of total bandwidth usage ( BW-Saving) to that of JM.…”

Section: Resultsmentioning

confidence: 99%

“…In our previous work of B R D analysis [9], we properly formulated ME operation with dynamic system bandwidth and determined the relationship between R D cost and system bandwidth. In this paper, the nonlinear B R D model provides a theoretical basis for system design and performance optimization in mobile multimedia applications.…”

Section: Proposed Frameworkmentioning

confidence: 99%

“…The target data bandwidth BW budget [9] for the current updated period (defined as P update ) is obtained from the smart memory controllers [12]. The frame-layer data bandwidth allocation for the ith frame is defined as…”

Section: B Proposed Me Algorithmmentioning

confidence: 99%

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Memory-efficient motion estimation design for mobile multimedia applications

Hsieh

Hung

Hsu

2015

2015 IEEE 5th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)

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In this paper, a novel motion estimation (ME) scheme with efficient memory design is presented for the mobile multimedia applications in H.264/AVC. To obtain the optimal memory usage and achieve better coding quality under volatile system operating conditions, we propose a novel bandwidth rate distortion (B R D) algorithm by exploring the motion activity properties of various video sequences. This scheme allocates the optimized data bandwidth into the corresponding coded block in a rate distortion sense using the convex optimization approach. The experimental results indicate that our proposed B R D ME algorithm can achieve up to 71% bandwidth savings for CIF size video.

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Section: Resultsmentioning

confidence: 99%

Section: Proposed Frameworkmentioning

confidence: 99%

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Memory-efficient motion estimation design for mobile multimedia applications

Hsieh

Hung

Hsu

2015

2015 IEEE 5th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)

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“…Furthermore, the selection between different search strategies makes the estimation more robust for different motion activities [5,6]. On the other hand, hardware architectures usually apply the full search (FS) due to its regularity [7][8][9][10][11][12][13][14][15]. This approach involves a great amount of hardware resources when the high throughput and the wide search range are required.…”

Section: Introductionmentioning

confidence: 99%

Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder

Pastuszak

Jakubowski

2015

J Sign Process Syst

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The adaptive computationally-scalable motion estimation algorithm and its hardware implementation allow the H.264/AVC encoder to achieve efficiencies close to optimal in real-time conditions. Particularly, the search algorithm achieves results close to optimum even if the number of search points assigned to macroblocks is strongly limited and varies with time. The architecture implementing the algorithm developed and reported previously takes at least 674 clock cycles to interpolate and load reference area, and the number cannot be decreased without decreasing the search range. This paper proposes some optimizations of the architecture to increase the maximal throughput achieved by the motion estimation system even four times. Firstly, the chroma interpolation follows the search process, whereas the luma interpolation precedes it. Secondly, the luma interpolator computes 128 instead of 64 samples per each clock cycle. Thirdly, the number of onchip memories keeping interpolated reference area is increased accordingly to 128. Fourthly, some modules previously working at the base frequency are redesigned to operate at the doubled clock. Since the on-chip memories do not store fractional-pel chroma samples, their joint size is reduced from 160.44 to 104.44 kB. Additional savings in the memory size are achieved by the sequential processing of two referencepicture areas for each macroblock. The architecture is verified in the real-time FPGA hardware encoder. Synthesis results show that the updated architecture can support 2160p@30fps encoding for 0.13 μm TSMC technology with a small increase in hardware resources and some losses in the compression efficiency. The efficiency is improved when processing smaller resolutions.

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“…In recent years, the speed gap between on-chip computing and off-chip memory access has grown larger and larger, so it is important to reduce off-chip bandwidth requirement to improve overall performance especially for real-time video applications [19]. Reusing data on chip is usually considered to reduce off-chip memory traffic.…”

Section: Introductionmentioning

confidence: 99%

High-Performance Motion Estimation for Image Sensors with Video Compression

Yin

Liu

et al. 2015

Sensors

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It is important to reduce the time cost of video compression for image sensors in video sensor network. Motion estimation (ME) is the most time-consuming part in video compression. Previous work on ME exploited intra-frame data reuse in a reference frame to improve the time efficiency but neglected inter-frame data reuse. We propose a novel inter-frame data reuse scheme which can exploit both intra-frame and inter-frame data reuse for ME in video compression (VC-ME). Pixels of reconstructed frames are kept on-chip until they are used by the next current frame to avoid off-chip memory access. On-chip buffers with smart schedules of data access are designed to perform the new data reuse scheme. Three levels of the proposed inter-frame data reuse scheme are presented and analyzed. They give different choices with tradeoff between off-chip bandwidth requirement and on-chip memory size. All three levels have better data reuse efficiency than their intra-frame counterparts, so off-chip memory traffic is reduced effectively. Comparing the new inter-frame data reuse scheme with the traditional intra-frame data reuse scheme, the memory traffic can be reduced by 50% for VC-ME.

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Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications

Cited by 8 publications

References 24 publications

Memory-efficient motion estimation design for mobile multimedia applications

Memory-efficient motion estimation design for mobile multimedia applications

Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder

High-Performance Motion Estimation for Image Sensors with Video Compression

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