Algorithm-based fault tolerance on a hypercube multiprocessor

Banerjee, P.; Rahmeh, J.T.; Stunkel, Craig B.; Nair, Vivek; Roy, Kaushik; Balasubramanian, Vijay; Abraham, Jacob A.

doi:10.1109/12.57055

Cited by 124 publications

(43 citation statements)

References 19 publications

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“…Some researchers have examined local reconfiguration techniques where a spare node can only replace a faulty node within a given subset [6], [7], [8], [9], [10], [11], [12], [13], [14]. The switch complexity of these schemes is similar to ours.…”

Section: Introductionmentioning

confidence: 78%

Enhanced cluster k-Ary n-cube, a fault-tolerant multiprocessor

Izadi

Özgüner²

2003

IEEE Trans. Comput.

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Abstract-In this paper, we present a strongly fault-tolerant design for the k-ary n-cube multiprocessor and examine its reconfigurability. Our design augments the k-ary n-cube with ð k j Þ n spare nodes. Each set of j n regular nodes is connected to a spare node and the spare nodes are interconnected as either a ð k j Þ-ary n-cube if j 6 ¼ k 2 or a hypercube of dimension n if j ¼ k 2 . Our approach utilizes the capabilities of the wave-switching communication modules of the spare nodes to tolerate a large number of faulty nodes. Both theoretical and experimental results are examined. Compared with other proposed schemes, our approach can tolerate significantly more faulty nodes with a low overhead and no performance degradation.

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Section: Introductionmentioning

confidence: 78%

Enhanced cluster k-Ary n-cube, a fault-tolerant multiprocessor

Izadi

Özgüner²

2003

IEEE Trans. Comput.

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“…Various algorithms implementing ABFT are available in the literature [37][38][39][40][41][42][43]. However, the disadvantage is that this technique should be tailored specifically for each algorithm, requiring time-consuming algorithm development.…”

Section: Algorithmic Based Fault Tolerance (Abft)mentioning

confidence: 99%

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Crop

Krimer

Moezzi-Madani

et al. 2011

JLPEA

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While Moore's law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit J. Low Power Electron. Appl. 2011, 1 335 approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.

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“…[10,7,12] to perform reconfiguration using spare nodes and spare links. In [12] two spares per 3-cube are assigned (Fig. 13) spares is now that of a simple switch.…”

Section: Fault-tolerant Hypercubesmentioning

confidence: 99%

“…To preserve the dimensionality of the faulty hypercube, hardware redundancy and spare allocation schemes [8,9,10,7,11,12,13,14,15] have been investigated.…”

Section: Fault-tolerant Hypercubesmentioning

confidence: 99%

Fault Tolerance in Hypercubes

Balakrishnan

Özgüner

Izadi

1993

Parallel Computing on Distributed Memory Multiprocessors

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This paper describes different schemes for tolerating faults in hypercube multiprocessors. A study of hypercube algorithms reveals that in many cases, the computations that require local communication are mapped onto topologies such as meshes or rings and the hypercube topology is used for global data communication. Therefore, a faulty hypercube needs to be reconfigured to perform both local and global communication as required by the algorithm, effectively and with minimal performance degradation. Two general approaches can be identified. The first approach looks into ways of utilizing the healthy processors and links of a hypercube with faulty nodes/links, for embedding topologies such as lower dimensional hypercubes, rings, meshes and trees for performing communication. The second approach makes use of hardware redundancy in the form of spare nodes and/or links and usually requires modifications in the communication hardware. Augmented hypercubes and spare allocation schemes are described.

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Algorithm-based fault tolerance on a hypercube multiprocessor

Cited by 124 publications

References 19 publications

Enhanced cluster k-Ary n-cube, a fault-tolerant multiprocessor

Enhanced cluster k-Ary n-cube, a fault-tolerant multiprocessor

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Fault Tolerance in Hypercubes

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