Algorithm design for a 30-bit integrated logarithmic processor

Lewis, David; Yu, Le

doi:10.1109/arith.1989.72826

Cited by 16 publications

(4 citation statements)

References 9 publications

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“…Partitioning optimization defines the number, size, and contents of small look-up tables that constitute the memory which stores the addition and subtraction function. Several LNS architectures for addition, subtraction, and multi-operand operations have been proposed in the literature using interpolation, linear, or polynomial approximation aiming at reducing the memory requirements, particularly for larger word lengths [27,28]. Furthermore mathematical decompositions and transformations of the basic operations, exploiting the particular characteristics of the functions, have been used to further simplify approximation [12,[27][28][29][30][31].…”

Section: A Design Methodology For Lns Systemsmentioning

confidence: 99%

Logarithmic Number System and Its Application in FIR Filter Design

Paliouras

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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Data representation is an important parameter in the design of digital signal processors as it affects their performance and hardware complexity. Data representation influences the choice of algorithms and the hardware architecture, thus it has an impact on data storage requirements, processing performance, complexity, and power dissipation [1][2][3].The Logarithmic Number System (LNS) can be used to efficiently represent data in special-purpose processors. The efficiency of LNS stems from the properties of the logarithm exploited to reduce the basic arithmetic operations of multiplication, division, square roots, and squares to simple binary addition, subtraction, and right and left shifts, respectively [4]. Similarly, the computation of general roots and powers as well as of reciprocals are substantially simplified.Building on the reduced complexity of certain arithmetic operations, digital signal processor implementations can benefit from substantial architectural-level simplifications. Furthermore, beyond operation strength reduction, superior LNS dynamic range and numerical behavior, compared to conventional representations, are additional reasons that make LNS attractive. In order to fully utilize LNS potential, procedures are required to optimally define LNS design parameters and derive LNS solutions, matched to application specifications and requirements.

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Section: A Design Methodology For Lns Systemsmentioning

confidence: 99%

Logarithmic Number System and Its Application in FIR Filter Design

Paliouras

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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“…Reference [23] uses only ROMs to compute the log() without any interpolation. The paper [22] use ROMs and linear tangent and/or secant interpolation. We are different from [19] and [22] in that we explore linear least squares based interpolation which gives us one extra bit of accuracy over our own linear secant implementation.…”

Section: Previous Workmentioning

confidence: 99%

“…The paper [22] use ROMs and linear tangent and/or secant interpolation. We are different from [19] and [22] in that we explore linear least squares based interpolation which gives us one extra bit of accuracy over our own linear secant implementation. Also our method lends itself elegantly to perform antilog() operation using the same hardware architecture and accuracy as log(), whereas [19], [22] do not talk about antilog() computation using the same hardware architecture as the log() computation.…”

Section: Previous Workmentioning

confidence: 99%

A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations

Paul

Jayakumar

Khatri

2009

IEEE Trans. VLSI Syst.

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Abstract-The realization of functions such as log() and antilog() in hardware is of considerable relevance, due to their importance in several computing applications. In this paper, we present an approach to compute log() and antilog() in hardware. Our approach is based on a table lookup, followed by an interpolation step. The interpolation step is implemented in combinational logic, in a fieldprogrammable gate array (FPGA), resulting in an area-efficient, fast design. The novelty of our approach lies in the fact that we perform interpolation efficiently, without the need to perform multiplication or division, and our method performs both the log() and antilog() operation using the same hardware architecture. We compare our work with existing methods, and show that our approach results in significantly lower memory resource utilization, for the same approximation errors. Also our method scales very well with an increase in the required accuracy, compared to existing techniques.Index Terms-Field-programmable gate arrays (FPGAs), floating point arithmetic, logarithmic arithmetic, VLSI.

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“…(It is interesting to note that table-lookup has also been discussed in connection with logarithmic arithmetic in Refs. [53,54].…”

Section: Arithmeticmentioning

confidence: 99%