An 8Kb content-addressable and reentrant memory

Kodata, H.; Miyake, J.; Nishimichi, Y.; Kudo, H.; Kagawa, K.

doi:10.1109/isscc.1985.1156820

Cited by 10 publications

(1 citation statement)

References 1 publication

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“…The priority encoder (PE) is a fundamental circuit in digital systems, having been used in many applications, such as content addressable memories [1], incrementer/decrementers [2], [3], interconnection network routers [4] and comparators [5], [6]. Consequently, a significant amount of literature is dedicated to deliver new designs with varying performance trade-offs [3], [6][7][8][9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Low-power, high-performance 64-bit CMOS priority encoder using static-dynamic parallel architecture

Balobas

Konofaos

2016

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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The performance of priority encoder circuits is usually limited by the delay associated with the propagation of the priority token, however, proper design in the architectural level can reduce the delay stages to the order of O(log n). Furthermore, power dissipation and area pose an increasingly important concern in modern circuit design, thus the development of suitable techniques is essential. This paper introduces a new 64-bit priority encoder based in a staticdynamic parallel priority lookahead architecture and a newly designed 4-bit PE cell. Compared to conventional works, it achieves up to 34% reduction in transistors, 80% reduction in power and 53% improvement in performance.

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Section: Introductionmentioning

confidence: 99%

Low-power, high-performance 64-bit CMOS priority encoder using static-dynamic parallel architecture

Balobas

Konofaos

2016

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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Content-addressable memory for VLSI pattern inspection

Chae¹,

Walker²,

Fu³

et al. 1988

IEEE J. Solid-State Circuits

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A ternary content addressable search engine

Wade¹,

Sodini

1989

IEEE J. Solid-State Circuits

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This paperdeseribes the design, implementation, and experimental results for a ternary content addressable search engine cfdp, known as the Database Accelerator (DBA). The DBA chip architecture is presented, and it is well suited to serve as a coprocessor for a variety of logical search applications. The core of the DBA system is composed of novel high-density content addressable memory (CAM) cells capable of storing three states. The design of these cells and their support circuitry is described. The CAM cell and support circuitry were fabricated and their operation confirmed. The circuit implementation of the DBA data path is described with particular emphasis on the optimization of the multiple response resolver. The timing and control methodology, which simultaneously satisfies the complexity, speed, and robustness requirements of the DBA chip, is reported. Fhally, experimental DBA chip results are presente@ these results verify the full functionality and testability of the design.

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An 8Kb content-addressable and reentrant memory

Cited by 10 publications

References 1 publication

Low-power, high-performance 64-bit CMOS priority encoder using static-dynamic parallel architecture

Low-power, high-performance 64-bit CMOS priority encoder using static-dynamic parallel architecture

Content-addressable memory for VLSI pattern inspection

A ternary content addressable search engine

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