An Accurate and Quick ANN-Based System-Level Dynamic Power Estimation Model Using LLVM IR Profiling for FPGA Designs

Tripathi, Abhishek; Rajawat, Arvind

doi:10.1109/les.2019.2935052

Cited by 7 publications

(4 citation statements)

References 9 publications

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“…After the system is powered on, the internal register of PLX9656 is reset by the RST\\\. At the same time, PLX9656 outputs local reset signal LRESET and checks whether EEPROM exists [16]. If the local DMA mode is used for control, the whole handshake process is as follows: First, when the energy data in the SDRAM cache reaches the set value, the signal is valid, and the PLX9656 sends an interrupt request signal to the host.…”

Section: Pci Logical Interfacementioning

confidence: 99%

Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

Luan

2022

International Transactions on Electrical Energy Systems

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In order to solve the problems of small signal acquisition range and poor acquisition accuracy of the existing multichannel acquisition system, a multisensor energy data fusion transformer acquisition system simulation method based on FPGA is proposed, and key hardware functions are designed and implemented. The system uses FPGA to control the core logic, synchronously collects and controls the energy data of the CCD camera and the laser rangefinder, organizes and uses an external large-capacity SDRAM group for buffering, and uses a dedicated PCI interface chip PLX9656 to achieve high-speed data transmission. Two pieces of sensor energy data and PCI bus energy data are stored in real time using a large-capacity disk array composed of multiple SATA hard disks. The function and performance of the energy data acquisition and storage system were tested. After the actual system test, the experimental results show that the transmission speed of the system through the PCI bus exceeds 200 MB/s, the writing speed of the continuous disk array is 240 MB/s, and the real-time acquisition and recording speed is 100 MB/ss. Conclusion. The system effectively solves the problems of high-speed data acquisition and storage and large capacity data transmission of key sensor nodes.

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Section: Pci Logical Interfacementioning

confidence: 99%

Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

Luan

2022

International Transactions on Electrical Energy Systems

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“…The hardware is responsible for dynamically scheduling blocks of threads to each compute unit of the GPU while ensuring that all threads of a block are executed on the same compute unit. This means that they can share the L1 cache and use the shared memory cache [13] , and the thread blocks themselves are executed on a series of wavefronts. That is a hardware 64-thread-wide SIMD unit with each wavefront being a series of threads.…”

Section: Dcu Architecturementioning

confidence: 99%

Compilation Optimization of DCU-oriented OpenMP Thread Scheduling

Zhou

Zhao

et al. 2023

J. Phys.: Conf. Ser.

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OpenMP is one of the mainstream parallel programming models in recent years. After version 4.0, OpenMP introduced a new target instruction to increase the functionality of heterogeneous programming, called OpenMP Offload. For the domestic heterogeneous platform DCU, the thread scheduling algorithm under OpenMP parallel computing has low performance in the default mode, which does not take the best advantage of GPU parallel computing and has wasted resources. To address this problem, this paper performs algorithm improvement at the compiler level, analyzes the available resources of the system by combining the DCU hardware facilities, then further parses the program based on its array information to get its program iteration number, reallocates the number of threads for different execution modes in OpenMP, and optimizes the thread group increase factor by combining the DCU hardware information to adjust the thread. This paper uses the SPEC ACCEL test set to optimize the number of threads in the DCU. In this paper, we use the SPEC ACCEL test set and Polybench standard test set to test the redistribution of threads and thread groups in two parallel modes using the thread scheduling optimization algorithm. The average speedup ratio of ACCEL was improved by 40%.

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“…Tripathi et al [147] introduce an MLP architecture to calculate power consumption, using LLVM IR instructions as input, and modelling only dynamic power.…”

Section: ) Modelsmentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed. INDEX TERMSComputing models, design space exploration, field programmable gate array (FPGA), system on chip (SoC), power consumption.years (2016-2022) and have been selected based on the topics addressed in this survey. Several papers published before 2016 have been considered because of their contributions to the current literature. C. OUTLINEThe remainder of this paper is organized as follows. Section II briefly presents the most widely used parallel computing models for CPU, GPU, and multicore processors. Section III introduces the FPGA-based reconfigurable hardware accelerator architectures, hardware/software co-design, DSE and metrics, and the techniques to improve latency, area, and power for this technology. In Section IV, we describe previous works on models, methodologies, and frameworks proposed for FPGA/SoC according to their main features: metrics estimation (IV-A), FPGA-based DSE (IV-B), and power consumption estimation (IV-C); and in Section IV-D, we present a summary and discussion. The integration of models and frameworks for FPGA-based reconfigurable hardware accelerators in different research fields is exposed in Section V. Challenges are analyzed in Section VI. Finally, conclusions are presented in Section VII. II. PARALLEL COMPUTING MODELS FOR PERFORMANCE ESTIMATIONComputing models allow to easily analyzing algorithms by simplifying the computational world to a reduced set of parameters that define the cost of arithmetic and memory access operations and communication. These models contribute to the search for efficient algorithms for a given architecture, improving the productivity of designers, programmers, and engineers. A small amount of communication, a small number of operations, and a high degree of parallelism are key points that d...

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An Accurate and Quick ANN-Based System-Level Dynamic Power Estimation Model Using LLVM IR Profiling for FPGA Designs

Cited by 7 publications

References 9 publications

Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

Compilation Optimization of DCU-oriented OpenMP Thread Scheduling

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

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