An Adaptive Balancing Modulation for Multilevel Diode Clamped Converters without Common Mode Voltage Injection

An Adaptive Multistep Balancing Modulation Technique for Multipoint-Clamped Converters

“…As in [35], the proposed approach imposes each αh to be proportional to the corresponding disbalance ∆vdc,h. By denoting with the subscript r the indexes of the voltage disbalances which can be equalized (i.e.…”

“…where VΣT is named Top Equivalent Balancing Voltage [35]. Similarly, by grouping with respect to σ and dN-1, one gets:…”

“…To overcome this drawback, other approaches [30][31][32][33][34][35]] employ a multiple-references/single-carrier comparison, which guarantees the independent control of each switching device and allows the output voltage to switch between many feasible levels in the same modulation period, thus exhibiting a Multi-Step behaviour. The main drawback here is represented by the increase of the switching losses and by a general worsening of the output voltage harmonic content, due to the presence of multiple switching transitions in each modulation interval.…”

“…This effect can be partially neutralized by adapting in real time the number of feasible switching levels to the converter's working conditions. This paper presents an improvement of the multi-step technique proposed by the authors in [35], where the adaptive choice of the switching levels was based on a feedback control loop acting on the worst DC-bus voltage disbalance. On the contrary, the adaptive technique described in the following is based on the real-time choice of the number of feasible switching levels in each modulation interval.…”

“…The proposed approach, described in Section II, has been particularized in Section III with respect to an MPC converter employed as an active High-Voltage-Direct-Current (HVDC) rectifier. The results, obtained through several Hardware-In-the-Loop (HIL) simulations, have shown how the proposed technique is able to sensibly reduce the switching transitions rate with respect both to the strategy proposed in [35] and to a baseline multi-step based approach discussed in [34], while at the same time supplying the desired average output voltages and keeping all the DC-bus capacitors voltages within a desired threshold. The conclusions of the work are drawn in Section IV.…”