An Analog Front-End IC Design for 320 &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\times$&lt;/tex-math&gt;&lt;/inline-formula&gt; 240 Microbolometer Array Applications

Seo, Il Won; Jung, Eun Sik; Sung, Man Young

doi:10.1109/tcsii.2015.2455391

Cited by 4 publications

(1 citation statement)

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“…Therefore, there is no need for a thermoelectric cooler that consumes additional power and volume. In addition, various readout integrated circuits (ROICs) for bolometer-type uncooled infrared image sensors using a standard CMOS process have been developed [12,13,14]. Among the various ROICs, the capacitive transimpedance amplifier (CTIA) is widely used to detect the signal output current of pixels [15].…”

Section: Introductionmentioning

confidence: 99%

Averaging Pixel Current Adjustment Technique for Reducing Fixed Pattern Noise in the Bolometer-Type Uncooled Infrared Image Sensor

Kim

Choi

Lee

et al. 2019

Sensors

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In this paper, we propose an averaging pixel current adjustment technique for reducing fixed pattern noise (FPN) in the bolometer-type uncooled infrared image sensor. The averaging pixel current adjustment technique is composed of active pixel, reference pixel, and calibration circuit. Polysilicon resistors were used in each active pixel and reference pixel. Resistance deviation among active pixels integrated with the same resistance value cause FPN. The principle of the averaging pixel current adjustment technique for removing FPN is based on the subtraction of dark current of the active pixel from the dark current of the reference pixel. The subtracted current is converted into the voltage, which contains pixel calibration information. The calibration circuit is used to adjust the calibration current. After calibration, the nano-ampere current is output with small deviation. The proposed averaging pixel current adjustment technique is implemented by a chip composed of a pixel array, a calibration circuit, average current generators, and readout circuits. The chip was fabricated using a standard 0.35 μm CMOS process and its performance was evaluated.

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