An Analytical Charge-Based Compact Delay Model for Submicrometer CMOS Inverters

Rosselló, Josep L.; Segura, J.

doi:10.1109/tcsi.2004.830692

Cited by 43 publications

(33 citation statements)

References 14 publications

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Section: Imentioning

confidence: 99%

“…Moreover, with continuous scaling down of transistor dimensions, the charging/discharging of input-output coupling capacitance (C M ) inevitably affects inverter characteristics and propagation delays, which should be considered in developing delay models [7,8,10,12,14,16,23].…”

Section: Imentioning

confidence: 99%

“…The reported propagation delay expressions for a submicron inverter are complex [8][9][10]14], which limits the exten-…”

Section: Imentioning

confidence: 99%

“…For extracting the propagation delay, development of a delay model for a CMOS inverter is considered as the first step [14], and a number of inverter delay models have been developed [6][7][8][9][10][11][12][13][14][15]. The first inverter delay expression was introduced by Burns [1].…”

Section: Introductionmentioning

confidence: 99%

“…With the increasing complexity of modern very large scale integration (VLSI) systems, transistor level simulation consumes much more computation time because of the nonlinear transfer characteristics of CMOS gates [8][9][10]. Therefore, an analytical delay model that does not need numerical iterations is needed to extract delay efficiently, and much work has been published on the topic [3,[6][7][8][9][10][11][12][13][14][15][16][17][18][19].For extracting the propagation delay, development of a delay model for a CMOS inverter is considered as the first step [14], and a number of inverter delay models have been developed [6][7][8][9][10][11][12][13][14][15]. The first inverter delay expression was introduced by Burns [1].…”

mentioning

confidence: 99%

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Analytical transient response and propagation delay model for nanoscale CMOS inverter

Wang

Zwoliński

2009

2009 IEEE International Symposium on Circuits and Systems

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Abstract−This paper presents a new analytical propagation delay model for a nanoscale CMOS inverter. By using a nonsaturation current model, the analytical input-output transfer responses and propagation delay model are derived. The model is used for calculating inverter delays with different input transition times, load capacitances and supply voltages. Delays predicted by proposed model are in good agreement with that of transistor level simulation results from SPICE, and errors are less than 3%. I.INTRODUCTION As one of the most important performance parameters in CMOS digital circuits, the propagation delay is of concern to designers and users. A circuit's speed/frequency and dynamic power dissipation are both affected significantly by propagation delay, and hence timing analysis has been investigated for several decades [1][2][3][4][5][6][7]. With the increasing complexity of modern very large scale integration (VLSI) systems, transistor level simulation consumes much more computation time because of the nonlinear transfer characteristics of CMOS gates [8][9][10]. Therefore, an analytical delay model that does not need numerical iterations is needed to extract delay efficiently, and much work has been published on the topic [3,[6][7][8][9][10][11][12][13][14][15][16][17][18][19].For extracting the propagation delay, development of a delay model for a CMOS inverter is considered as the first step [14], and a number of inverter delay models have been developed [6][7][8][9][10][11][12][13][14][15]. The first inverter delay expression was introduced by Burns [1]. Early models were based on Shockley's square law MOSFET model which does not include the carrier velocity saturation effect [1,2]. As the drain current (I ds ) deviates significantly from the Shockley model in the submicron region, Sakurai et al. [3] proposed a model using an α-power law current model which includes the carrier velocity saturation effect of short channel devices. Several analytical delay expressions based on the α-power law model were introduced thereafter [10, 13]. However, in modern small dimension MOSFETs, I ds does not show saturation [20][21][22]. Therefore, α-power law based delay models would underestimate inverter propagation delay by using higher I ds (at V ds =V dd ) as the saturation current in the nominal saturation region.On the other hand, some delay models did not take the current through the loading transistor into account [3, 13], including both the overshooting and short-circuit current [10,14,23]. Moreover, with continuous scaling down of transistor dimensions, the charging/discharging of input-output coupling capacitance (C M ) inevitably affects inverter characteristics and propagation delays, which should be considered in developing delay models [7,8,10,12,14,16,23].The reported propagation delay expressions for a submicron inverter are complex [8][9][10]14], which limits the exten-

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Section: Imentioning

confidence: 99%

Section: Imentioning

confidence: 99%

“…The reported propagation delay expressions for a submicron inverter are complex [8][9][10]14], which limits the exten-…”

Section: Imentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Analytical transient response and propagation delay model for nanoscale CMOS inverter

Wang

Zwoliński

2009

2009 IEEE International Symposium on Circuits and Systems

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A high precision close‐loop programmable CMOS delay generator for UWB and time domain RF applications

Nguyen

2010

Micro & Optical Tech Letters

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This article presents a novel programmable high precision delay generator with adjustable digital control for ultrawideband and time-domain RF applications. Ring oscillator based phase locked loop (PLL) is embedded to achieve desired propagation delay in the delay cell against process, temperature, and power supply variations. A replica inverter delay line parallel to the PLL offers a separate delay path for input clock. Sub-nanosecond delay step with high accuracy can be obtained by shaping the input clock slope and keeping a careful matching between the replica delay line and the delay cell in PLL. The prototype of the delay generator is implemented on a 0.18-lm CMOS process. The measurement results show relative delay error of 0.8%. The circuit consumes 9.5 mA from a 1.8-V power supply.

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Modeling the Operation of CMOS Primitive Circuits and MOSFET Devices

Bisdounis¹

2013

System-Level Design Methodologies for Telecommunication

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An Analytical Charge-Based Compact Delay Model for Submicrometer CMOS Inverters

Cited by 43 publications

References 14 publications

Analytical transient response and propagation delay model for nanoscale CMOS inverter

Analytical transient response and propagation delay model for nanoscale CMOS inverter

A high precision close‐loop programmable CMOS delay generator for UWB and time domain RF applications

Modeling the Operation of CMOS Primitive Circuits and MOSFET Devices

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