An analytical placer for heterogeneous FPGAs via rough-placed packing

Wu, Wan-Ning; Chen, Chen; Chin, Ching-Yu; Wang, Chun-Kai; Chen, Hung-Ming

doi:10.1109/vlsi-dat.2017.7939659

2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 2017

DOI: 10.1109/vlsi-dat.2017.7939659

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An analytical placer for heterogeneous FPGAs via rough-placed packing

Wan-Ning Wu

Chen Chen

Ching-Yu Chin

et al.

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An analytical placer for heterogeneous FPGAs via rough-placed packing

Cited by 0 publications

References 16 publications

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