An approach for customizing on-chip interconnect architectures in SoC design

Chariete, Abderrahim; Bakhouya, Mohamed; Gaber, Jaafar; Wack, Maxime

doi:10.1109/hpcsim.2012.6266926

Cited by 6 publications

(2 citation statements)

References 23 publications

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“…Many studies have shown that, to improve the performance of specific application domain, OCI architectures have to be customized at design-time by, for example, inserting additional longrange links between switches or allocating only required buffer size [1,13,23]. These approaches are generally tailored a specific application by providing an application specific SoC [24].…”

Section: Packet Switched Ocismentioning

confidence: 99%

A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs

et al. 2015

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Section: Packet Switched Ocismentioning

confidence: 99%

A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs

et al. 2015

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“…In order to improve the performance of specific application domain, OCI architectures are customized at design-time by inserting additional long-range links between switches or allocating only required buffer size [10,11]. There is no universal OCI, which could support all SoC application traffic patterns.…”

Section: Related Workmentioning

confidence: 99%

FracNoC: A fractal on-chip interconnect architecture for System-on-Chip

Chariete

Bakhouya

Gaber

et al. 2013

2013 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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Sophisticated on-chip interconnects (OCIs) were recently proposed as a solution to non-scalable shared bus schemes for Systems-on-Chip (SoC) design and implementation. In this paper a new OCI architecture by adapting a fractal topology structure is introduced. Simulations were conducted to compare this topology with two common OCIs, 2D Mesh, and Torus, using a variety of traffic patterns. Results show that this fractal architecture achieves better performance while using little energy budget. Network on Chip; System on Chip; Fractal structures; simulations; performance evaluation; Nirgam I.978-1-4799-0838-7/13/$31.00 ©2013 IEEE

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A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Xiao

Baas

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Network-on-Chips (NoCs) are used to connect large numbers of processors in many-core processor architecture because they perform better than less scalable methods such as global shared buses. Among all NoC design parameters, NoC topologies define how nodes are placed and connected and greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Due to its simplicity and the fact that processor tiles are traditionally square or rectangular, 2D mesh is mostly used for existing on-chip networks. However, efficiently mapping applications can be a challenge for cases that require communication between processors that are not adjacent on the 2D mesh. Motivated by the fact that applications often have largely localized communication patterns, we have proposed an 8-neighbor mesh topology and a 6-neighbor topology with hexagonal-shaped processor tiles, both of which increase local connectivity while keep much of the simplicity of a mesh-based topology. We have physically designed a 16-bit DSP processor and the corresponding processor arrays which utilize all three topologies. A 1080p H.264/AVC residual video encoder and a 54 Mbps 802.11a/11g OFDM wireless LAN baseband receiver are mapped onto all topologies. The 6-neighbor hexagonal grid topology incurs a 2.9% area increase per tile compared to the 4-neighbor 2D mesh, but its much more effective interprocessor interconnect yields an average total application area reduction of 21%, an average power reduction of 17%, and a total application interprocessor communication distance reduction of 19%.

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An approach for customizing on-chip interconnect architectures in SoC design

Cited by 6 publications

References 23 publications

A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs

A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs

FracNoC: A fractal on-chip interconnect architecture for System-on-Chip

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

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