An approach to instruction scheduling at the processor architecture level for optimizing embedded software

Pham, Van Huong; Bui, Ngoc Hai; Nguyen, Ngoc Binh

doi:10.1109/atc.2014.7043388

2014 International Conference on Advanced Technologies for Communications (ATC 2014) 2014

DOI: 10.1109/atc.2014.7043388

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An approach to instruction scheduling at the processor architecture level for optimizing embedded software

Van Huong Pham

Ngoc Hai Bui

Ngoc Binh Nguyen

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2024

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Energy-Aware Register Allocation for VLIW Processors

Stuckmann,

Weißbrich,

Payá-Vayá

2024

J Sign Process Syst

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The efficiency of VLIW processors can be improved by reducing the energy consumption associated with accessing the register-file. This paper presents an energy-aware register allocation approach to reduce the dynamic energy consumption of a scheduled program by using an evolutionary algorithm approach and a register access transition energy model. Additionally, the influence of instruction scheduling on energy-aware register allocation is analyzed. By using the proposed energy-aware compiler backend on synthetic applications with random data in the register-file, the dynamic energy consumption of the total processor core for an exemplary VLIW processor can be reduced by up to $$\varvec{21\%}$$ 21 % compared to a heuristic register allocation. In real-world applications from the domain of hearing aids, energy consumption can be reduced by up to $$\varvec{42.7\%}$$ 42.7 % for single applications, and $$\varvec{17.6\%}$$ 17.6 % average across a range of applications.

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Energy-Aware Register Allocation for VLIW Processors

Stuckmann,

Weißbrich,

Payá-Vayá

2024

J Sign Process Syst

View full text Add to dashboard Cite

show abstract

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An approach to instruction scheduling at the processor architecture level for optimizing embedded software

Cited by 1 publication

References 8 publications

Energy-Aware Register Allocation for VLIW Processors

Energy-Aware Register Allocation for VLIW Processors

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