An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

Abstract

In this paper, we propose a uni¯ed architecture for computation of double-precision°oatingpoint division, reciprocal, square root, inverse square root and multiplication with a signi¯cant area reduction. First, a double-precision multiplication-based divider, the common datapath shared with these arithmetic computations, is optimized by a modi¯ed Goldschmidt algorithm to achieve better area e±ciency. In this algorithm, a linear-degree minimax approximation instead of second-degree is used to obtain a 15-bit precision estimate of the reciprocal so that we can get a rather small lookup table (LUT) as well as reduced amount of computation when accumulating the partial products. Two Goldschmidt iterations specially designed for hardware reuse are performed to gain the¯nal accurate result of division. By virtue of the pipelined processing, the time cost for the two iterations is minimized. Second, a recon¯gurable datapath with a little extra area cost is introduced to dynamically support multiple double-precision computations by executing the optimized divider iteratively. The design is¯nally implemented and synthesized in SMIC 0.13-m CMOS process. The experimental results show that the proposed design can achieve a speed of 400 MHz with area of 61.6 K logic gates and 9-Kb LUT. Compared with other works, the area e±ciency (performance/area ratio) of the proposed uni¯ed architecture is increased by about 20% in average, which is a better performance-area trade-o® for embedded microprocessors.