An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder

Dhanasekar, S.

doi:10.1080/00207217.2023.2278434

Cited by 8 publications

(2 citation statements)

References 43 publications

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“…Because of Cout is not depended on the input carry Cin. Also, horizontal and vertical signal paths of compressors are simple and regular structure than other existing technique 14 .…”

Section: Compressormentioning

confidence: 99%

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Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

Thamizharasan,

Parthipan

2024

Sci Rep

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In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).

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“…Because of Cout is not depended on the input carry Cin. Also, horizontal and vertical signal paths of compressors are simple and regular structure than other existing technique 14 .…”

Section: Compressormentioning

confidence: 99%

“…In that selection input of multiplexer (MUX) is 13 . It achieves the critical path delay of 3 XOR gate delay 14 .…”

Section: :2 Compressormentioning

confidence: 99%

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

Thamizharasan,

Parthipan

2024

Sci Rep

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A novel hybrid fast Fourier transform processor in 5G+ and bio medical applications

Priyadharsini,

Sasipriya

2024

Microprocessors and Microsystems

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Design of energy efficient N-bit vedic multiplier for low power hardware architecture

Sridevi,

Sathiya

2024

International Journal of Electronics

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An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder

Cited by 8 publications

References 43 publications

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

A novel hybrid fast Fourier transform processor in 5G+ and bio medical applications

Design of energy efficient N-bit vedic multiplier for low power hardware architecture

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