An ASIC CAM design for associative set processors

Abstract

One of the key requirements in systems for symbolic computation is the fast and efficient execution of set operations, such as addition, removal, or test for membership of an element in a given set S . Contentaddressable memory (CAM) offers the potential for massive fine-grained parallelism in the implementation of these operations, yielding a potential speedup of O(I SI). This paper describes an ASIC design of a 32x32 CMOS static CAM for use in an associative set processor.