An Asymmetric Adaptive SCL Decoder Hardware for Ultra-Low-Error-Rate Polar Codes

Abstract

In theory, Polar codes do not exhibit an error floor under successive-cancellation (SC) decoding. In practice, frame error rate (FER) down to 10 −12 has not been reported with a real SC list (SCL) decoder hardware. This paper presents an asymmetric adaptive SCL (A2SCL) decoder, implemented in real hardware, for high-throughput and ultra-reliable communications. We propose to concatenate multiple SC decoders with an SCL decoder, in which the numbers of SC/SCL decoders are balanced with respect to their area and latency. In addition, a novel unequal-quantization technique is adopted. The two optimizations are crucial for improving SCL throughput within limited chip area. As an application, we build a link-level FPGA emulation platform to measure ultra-low FERs of 3GPP NR Polar codes (with parity-check and CRC bits). It is flexible to support all list sizes up to 8, code lengths up to 1024 and arbitrary code rates. With the proposed hardware, decoding speed is 7000 times faster than a CPU core. For the first time, FER as low as 10 −12 is measured and quantization effect is analyzed.

An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture

“…The difference of decoding latency and error-correction performance between SC decoding and SCL decoding should be taken into account. However, different from the method proposed in [22], the decoding latency varies with different deployments, as the SC decoding and SCL decoding share the common PEs. That is to say, the speed gain β of SC decoding relative to SCL decoding is not a fixed value.…”

“…In order to guarantee the excellent decoding performance, an SCL decoding with list size L = 16 is adopted in hybrid mode. As proposed in [22], an asymmetric hybrid decoder can balance the workload between SC decoder and SCL decoder. Hence, we instantiate more cores than the list size in our design so that the rest decoding cores can be used for SC decoding while SCL decoding.…”

“…In the current design of hybrid polar decoder [21], [22], most of the time the utilization ratio of PEs is very low. Hence, in our design, different decoding cores share one common processing array to improve the utilization ratio.…”

“…The average list sizeL is reduced due to most codewords can be correctly decoded by the small list decoder. Besides, in recent research, an asymmetric adaptive SCL with several SC decoders and one SCL decoder was proposed in [22] to improve the utilization ratio of SCL decoder. In this hybrid decoder, the difference between an SC decoder and an SCL decoder in terms of computational complexity and workload is considered.…”

“…To support large list size and code length, another hybrid polar decoder was proposed in [27] with three inner decoders: one SC decoder for long code length, one SCL decoder with a flexible list size and one ultra-reliable SCL decoder with list size L = 32. Later, in [22], a load-balanced hybrid polar decoder was proposed, considering the difference between the SC decoder and the SCL decoder. However, in these designs, they only made several optimization techniques for internal LLRs message storage [28], [29], but not considered the optimization for processing elements (PEs).…”