2011 24th Internatioal Conference on VLSI Design 2011
DOI: 10.1109/vlsid.2011.69
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An Automated Approach for Minimum Jitter Buffered H-Tree Construction

Arup Mandal
1
,
Nikhil Jayakumar
2
,
Kalyana C. Bollapalli
3
et al.
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Cited by 3 publications
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A low-jitter phase-locked resonant clock generation and distribution scheme

Mandal
1
,
Bollapalli
2
,
Jayakumar
3
et al. 2013
2013 IEEE 31st International Conference on Computer Design (ICCD)
3
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1
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A low-jitter phase-locked resonant clock generation and distribution scheme

Mandal
1
,
Bollapalli
2
,
Jayakumar
3
et al. 2013
2013 IEEE 31st International Conference on Computer Design (ICCD)
3
0
1
0
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Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems

Stow
1
,
Akgun
2
,
Xie
3
2019
2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
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3
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Generic methodolgy and solution for Additive Jitter correction in Mesh based clock architectures

Santhanam,
Dhole,
Anumala
2024
2024 28th International Symposium on VLSI Design and Test (VDAT)
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