An automated, FPGA-based reconfigurable, low-power RFID tag

Jones, Alex K.; Hoare, Raymond R.; Dontharaju, Swapna; Tung, Shenchih; Sprang, Ralph; Fazekas, J.; Cain, James T.; Mickle, Marlin H.

doi:10.1016/j.micpro.2006.03.002

Cited by 35 publications

(17 citation statements)

References 10 publications

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“…The power comparisons of tag chips are ranged from several hundreds to ten-kilos of lW consumption using a commercial process [39]. Focus on power dissipation of Manchester encoder/decoder, 950 lW in Spartan-3 realization and 284-lW using 0.16 lm process were proposed [40]. In this work, the power consumption of the encoder core is estimated as only order of several ten of lW working in a higher data rate.…”

Section: Coding Schemesmentioning

confidence: 99%

Time-interleaved CMOS chip design of Manchester and Miller encoder for RFID application

Hung

2012

Analog Integr Circ Sig Process

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In this paper, we propose a modified Manchester and Miller encoder that can operate in high frequency without a sophisticated circuit structure. Based on the previous proposed architecture, the study has adopted the concept of parallel operation to improve data throughput. In addition, the technique of hardware sharing is adopted in this design to reduce the number of transistors. This circuit is realized by using TSMC CMOS 0.35-lm 2P4M technologies. The simulation results of HSPICE indicate that it functions and works successfully at 200-MHz data rate. An experimental chip had been fabricated and measured. The measured results show that the experimental chip has 50 MHz data throughput rate under 3.3-V supply voltage. The lowest supply voltage 0.6 V is achievable working at 5 kHz data rate. The average power consumption of the circuit under room temperature is 549 lW. The chip area is 70.7 lm 9 72.2 lm. The compact structure and high-speed operation are useful for radio frequency identification applications.

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Section: Coding Schemesmentioning

confidence: 99%

Time-interleaved CMOS chip design of Manchester and Miller encoder for RFID application

Hung

2012

Analog Integr Circ Sig Process

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“…Its functionality is examined both in simulations and in a measurement environment. This approach is followed for instance in the study by [35,37,57,58] for RFID tags or in [42,59] for RFID readers. Furthermore, the approach of an automatic generation of hardware modules out of highlevel descriptions, as it is common practice in chip design [60], is demonstrated on the example of encoding and decoding units in RFID [61,62].…”

Section: Rapid Prototyping Environments For Rfidmentioning

confidence: 99%

Evaluation and exploration of RFID systems by rapid prototyping

Angerer¹,

Langwieser²,

Rupp³

2011

Pers Ubiquit Comput

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Today's RFID systems exhibit relatively little functionality, while future systems and ubiquitous computing applications require an ample set of general purpose features, like wide communication ranges, high data rates, high reliability, and many more. In order to meet these high-performance goals, several challenges in state of the art RFID systems need to be managed: (1) the compatibility of RFID equipment, working according to different standards in various frequency domains, (2) the thorough understanding of the performance impact of physical layer system parameters, (3) the venture of novel wireless technologies in the context of RFID, and finally, (4) to deal with the increased complexity of high-performance RFID systems. Therefore, designers desire a highly configurable, flexible, and high-performance RFID environment to experimentally explore the underlying physical conditions and to evaluate novel RFID technologies and designs. This paper introduces the concept of rapid prototyping in RFID and provides a survey of system simulators, demonstrators, and rapid prototyping environments. A guideline for the setup for such a rapid prototyping system applicable for RFID is presented, and its implementation is demonstrated. Finally, some exemplary measurements carried out with this rapid prototyping system are presented.

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“…Closed-loop applications have mainly been adopted to comply with client mandates, where the majority of suppliers have followed the "slap-and-ship" approach, in which RFID tags are put on products before they leave a warehouse and are sent to retailers. This represents an increased cost for the supplier since it does not exploit the benefits of RFID within their facilities and usually implies the usage of proprietary solutions, thereby increasing the cost of deployment and the raising of compatibility issues among supplychain members (Stroh and Ringbeck, 2004;Jones et al, 2007). Indeed, according to Watson (2005, in Hingley et al, 2007, some of Wal-Mart's suppliers have spent an average of US$500 000 to conform with the demand to implement RFID-enabled shipments of cases and pallets.…”

Section: Justification Of Investmentmentioning

confidence: 99%