An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering

Ahmed, Zakir K.; Krishnamurthy, Harish K.; Weng, Sheldon; Liu, Xiaosen; Schaef, Chris; Desai, Nachiket; Ravichandran, Krishnan; Tschanz, James; De, Vivek

doi:10.1109/vlsicircuits18222.2020.9162827

Cited by 1 publication

(5 citation statements)

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“…Hence, the required number of inductors is also increased. On the contrary, each inductor's required footprint does not scale down, posing a severe challenge in integrating these inductors [56]. Therefore, the FIVRs are not suitable to achieve efficient power delivery and power management in multi-core SoCs because of their huge area overhead.…”

Section: B Fully Integrated Reconfigurable Pdn (Rpdn)mentioning

confidence: 99%

“…To overcome the area constraints of the PDN using FIVRs only, a fully integrated autonomous reconfigurable PDN (RPDN) was recently proposed [56]. As shown in Fig.…”

Section: B Fully Integrated Reconfigurable Pdn (Rpdn)mentioning

confidence: 99%

“…9, this RPDN reduces the number of FIVRs to just two. Each FIVR is dynamically shared among four co-located cores via per-core DLDOs [56]. Each per-core DLDO consists of a local LDO control (LLC) block, which controls two local power gates (PGs), as shown in Fig.…”

Section: B Fully Integrated Reconfigurable Pdn (Rpdn)mentioning

confidence: 99%

“…With these techniques, the 2-input/4-output RPDN shown in Fig. 9 delivers a better performance on demand while maximizing the overall energy efficiency along with better core count and scalability [56]. However, the fully integrated RPDN using on-chip inductors still occupies a significant valuable area on the package, conflicting with the stringent requirements of modern enterprise microprocessors [55].…”

Section: B Fully Integrated Reconfigurable Pdn (Rpdn)mentioning

confidence: 99%

“…Simplified block diagram of fully-integrated autonomous reconfigurable PDN using 2 FIVRs and 4 LDOs[56].…”

mentioning

confidence: 99%

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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Conventional power delivery networks (PDNs) and power management techniques using off-chip power converters with bulky passive components cannot meet the ever-evolving power delivery requirements of high-performance modern system-on-chips (SoCs). In SoCs, heterogeneous components, including multi-core processors and mixed-signals peripheral circuits, require state-of-the-art PDNs to provide high-quality power-on-demand with minimum latency, simultaneously achieving the small-factor, high conversion efficiency, and minimum current consumption. To satisfy these power delivery requirements, various PDNs have been developed over the past decades, such as the conventional architectures using off-chip power converters, architectures using in-package power converters and fully-integrated power converters, and heterogeneous architectures (off-chip power converters and on-chip regulators). This paper reviews these architectural advancements of the PDNs and their advantages and limitations, which leads us to discuss a heterogeneous PDN structure consisting of a highly efficient off-chip switching-mode power converter and multiple highly precise small linear regulators integrated on chip at point-of-load locations. The heterogeneous PDN has been proved one of the most suitable architectures to achieve high-quality finegrained on-chip power delivery and management in SoCs. This paper also discusses unified voltage and frequency regulators (UVFRs), which support dynamic-variation-aware dynamic voltage and frequency scaling (DVFS) for fine-grained power management in multi-core processors. Based on the UVFR, we propose a modified heterogeneous PDN using frequency-referenced digital low-dropout regulators (FR-DLDOs) for more efficient DVFS, eliminating the need for band-gap circuits to provide reference voltages. As an exemplary implementation of FR-DLDO for this PDN, we present an FR-DLDO with a transientboost control, which accelerates the transient response. The transient-boost control is activated dynamically only when an abrupt change happens out of the steady state. The implemented FR-DLDO fabricated in a 40-nm CMOS process outperforms other FR-DLDOs in the figure-of-merit and peak power efficiency while driving 40 mA of load current. INDEX TERMS Power delivery network (PDN); fine-grained power management; dynamic-voltage and frequency scaling (DVFS); dynamic-voltage scaling (DVS); low-dropout regulator (LDO); digital LDO; unified-voltage and frequency regulator (UVFR); frequency-referenced digital LDO (FR-DLDO); transientboost control.

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Section: B Fully Integrated Reconfigurable Pdn (Rpdn)mentioning

confidence: 99%

“…To overcome the area constraints of the PDN using FIVRs only, a fully integrated autonomous reconfigurable PDN (RPDN) was recently proposed [56]. As shown in Fig.…”

Section: B Fully Integrated Reconfigurable Pdn (Rpdn)mentioning

confidence: 99%

Section: B Fully Integrated Reconfigurable Pdn (Rpdn)mentioning

confidence: 99%

Section: B Fully Integrated Reconfigurable Pdn (Rpdn)mentioning

confidence: 99%

“…Simplified block diagram of fully-integrated autonomous reconfigurable PDN using 2 FIVRs and 4 LDOs[56].…”

mentioning

confidence: 99%

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