An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards

Chen, Zhixiang; Zhao, Xiongxin; Peng, Xiao; Zhou, Dajiang; Goto, Satoshi

doi:10.1109/iscas.2010.5537638

Cited by 14 publications

(10 citation statements)

References 5 publications

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“…The counter CNT is incremented at the end of the current iteration if CNMM is decreased and SYN is increased w.r.t. previous iteration (lines [11][12][13][14][15]. When CNT reaches threshold It ESC , 'impossible decoding' is detected and the decoder is stopped (lines [16][17].…”

Section: Msescmentioning

confidence: 99%

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Energy‐efficient multi‐standard early stopping criterion for low‐density‐parity‐check iterative decoding

2014

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International audienceLow-density-parity-check codes decoding relies on powerful iterative algorithms, whose implementation is often expensive in terms of complexity and power consumption. Several early stopping criteria (ESCs) have been proposed to reduce the number of iterations performed by a decoder with no (or limited) degradation of error correction performance. However, most of the existing ESCs have considered a reduced set of system parameters for validation and often have ignored the impacts related to a real hardware implementation. This study proposes a novel multi-standard early stopping criterion (MSESC) able to adapt dynamically to changes of code parameters, quantisation and channel conditions. A dedicated hardware architecture is devised and integrated in a multi-standard decoder, and compared with existing techniques. Post-layout results of the proposed MSESC show a small area increment (+1.3%) and a large decrement of the average energy consumption (up to 87.2%) with respect to the same decoder implemented with no ESC. Moreover, it is shown that MSESC offers an energy consumption reduction with respect to the state-of-the-art ESCs ranging from 4% [at high signal-to-noise ratio (SNR)] to 16% (at low SNR)

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Section: Msescmentioning

confidence: 99%

“…Incorporation of early stopping criteria (ESC) in an iterative LDPC decoder enables energy saving by limiting the average number of decoding iterations [15][16][17][18][19]. In this approach, the evolution of a certain metric is analysed over the iterations and a proper stopping rule is set.…”

Section: Introductionmentioning

confidence: 99%

Energy‐efficient multi‐standard early stopping criterion for low‐density‐parity‐check iterative decoding

2014

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“…In [79], two methods aimed at reducing power and increasing throughput are studied and implemented. The first one is the iteration earlystopping (ES) criterion proposed in [80], that allows to stop the decoding when all the information bits of a codeword are correct, regardless of the redundancy bits. The other is a threshold-based message stopping (MS) criterion, that reduces the traffic load on the network by avoiding injection of values which carry information about high-probability correct bits.…”

Section: Bandwidth and Power Reductionmentioning

confidence: 99%

Flexible LDPC Decoder Architectures

Awais

Condo

2012

VLSI Design

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Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.

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“…As the iterative decoding process consumes huge energy, these LDPC decoders require an early termination (ET) scheme for terminating redundant iterations. In the literature, several well‐known ET schemes, such as the hard‐decision aided (HDA) [12], soft‐decision aided (SDA) [13], and parity‐check equation (PCE) [14] schemes, were adopted for reducing LDPC decoding iterations by examining the data reliability. The layered stopping (LS) criterion [15] and the check node stopping criterion [16] were proposed for further terminating the decoding operations within the unterminated iterations.…”

Section: Introductionmentioning

confidence: 99%

Energy‐efficient LDPC codec design using cost‐effective early termination scheme

Lin¹,

Wu²,

Song³

2018

IET Computers & Digital Techniques

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Here, the authors propose an energy-efficient codec design using a rate-0.91 systematic quasi-cyclic-low-density parity-check (QC-LDPC) code. A cost-effective early termination (ET) scheme is presented for efficiently terminating the decoding iterations and maintaining desirable correcting performance. Compared with no ET scheme, the cost-effective ET scheme achieves 54.6% energy reduction with 1.7% area overhead. Finally, the proposed QC-LDPC codec employing the costeffective ET scheme is implemented in a prototyping chip of 9.86 mm 2 core area using the TSMC 90 nm CMOS technology. Compared with the other decoder chips, the prototyping codec operating at 278 MHz achieves the best decoding energy efficiency of 156 pJ/bit with a high decoding throughput of 4.3 Gbps. The prototyping codec also achieves a high encoding throughput of 4.4 Gbps.

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An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards

Cited by 14 publications

References 5 publications

Energy‐efficient multi‐standard early stopping criterion for low‐density‐parity‐check iterative decoding

Energy‐efficient multi‐standard early stopping criterion for low‐density‐parity‐check iterative decoding

Flexible LDPC Decoder Architectures

Energy‐efficient LDPC codec design using cost‐effective early termination scheme

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