1999
DOI: 10.1155/2000/71046
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An Edge‐endpoint‐based Configurable HardwareArchitecture for VLSI Layout Design Rule Checking

Abstract: Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking (DRC) were hobbled by the fact that it is often impractical to build a different rulechecking ASIC each time design rules or fabrication processes change. In this paper, we propose a configurable hardware approach to DRC. It can garner impressive speedups over software approaches, while retaining the flexibility needed to change the rule checker as rules or processes change.Our work proposes an edge-endpoints-based method for … Show more

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