An Effective Block Pin Assignment Approach for Block-Level Monolithic 3-D ICs

Abstract

In a 2D design, the block pins are located at the periphery of a block optimally since blocks are placed side-byside horizontally in a single placement layer. However, Monolithic 3D (M3D) integration relieves this boundary constraint by allowing vertical block communication between different tiers based on a nm-scale pitch of 3D interconnection. In this article, we present a design methodology named Pin-in-the-Area that assigns block pins at any position inside the boundary of a block using commercial 2D P&R tools, and enables an efficient block implementation and integration for a block-level M3D ICs. Our Pin-in-the-Area starts from the netlist restructuring and connectivity-aware tier-by-tier chip planning, which define blocks and decide their sizes and (X, Y, Z) locations for a two-tier M3D design. Next, we perform wirelength-driven 3D placement to minimize 3D half-perimeter wirelength and find optimal pin locations inside the boundary of a block. Once block designs are done, we apply the unique macro handling scheme to the top-level timing closure. Based on a 28nm two-tier M3D hierarchical design result, we show that our solution offers 13.6% and 24.7% energy-delay-product reduction compared to the M3D design with pins assigned at the block boundaries and its 2D counterpart, respectively. Index Terms-3D integrated circuits, physical design (EDA), block-level design, block pin assignment, Pin-in-the-Area.