An Efficacious Runtime Adaptive Hybrid Dram/Pram Memory in FPGA Platform

Abstract

Hybrid main memory comprising of DRAM and PRAM becomes quite popular because of the less standby power benefit of PRAM and high performance of DRAM. In this work, the runtime-adaptive control and DRAM bypassing methods are introduced in order to minimize DRAM refresh energy that occupies a considerable portion of total system power. The work is carried out by using Xilinx 12.1 simulation tool and the experimental result proves that in the proposed work power consumption is greatly reduced i.e., only requires 3 %, with less area overhead while maintaining the speed parameter by comparing with the conventional method .