An efficient 3D IC partitioning approach using satin bowerbird optimization for reduced TSV count and improved heat dissipation

Abstract

Net list partitioning achieves paramount importance in the physical architecture design step of Three Dimensional (3D) Very Large Scale Integrated (VLSI) circuits. The performance of all subsequent steps like floor layout, placement, pin assignment, and routing in the physical architecture design of the VLSI circuit are heavily affected by the outcomes of partitioning steps. Wire length between gates is reduced by 3D Integrated Circuit (IC) due to compact footprint as well as vertical inter connections among dies. This reduced wire length in turns responsible for less energy consumption and reduced connection delays. In this paper, Satin Bowerbird Optimization (SBO) is applied to solve 3D IC partitioning challenges. The suggested 3D IC partitioning technique is aimed at reducing the number of Through Silicon Vias (TSV) and measurements have also been taken to reduce heat dissipation. The presence of a significant amount of TSVs expands the chip area. 3D ICs have considerably greater densities of power because of advances in the technology and a vastly increased variety of components with high frequency. The heat generated by the used power has an impact on the performance and dependability of the chip. In this experiment, SBO is used as a multi-objective optimization method to achieve two objectives simultaneously - TSV count minimization and heat dissipation reduction. The performance of the suggested SBO - based approach is assessed utilizing the Giga Scale Research Center (GSRC) benchmark circuits. The applicability of the suggested technique is judged by comparing the outcomes with thermal-aware multilevel hyper-graph partitioning method. The findings of the comparison reveal that the suggested technique outperforms the thermal-aware multilevel hyper-graph partitioning approach by lowering the number of TSV count, maximum area requirement, and power density by 16.99%, 9.94% and 29.10% respectively. The performance of the experiment is also compared with existing Simulated Annealing and Tabu search based techniques. In both cases, the proposed method achieves better result by lowering TSV by 26.03% and 27.31%, and reducing area by 6.59% and 6.59%, respectively.