An Efficient 5-Transistor SRAM Cell Design using FNSBS-CNTFET for Improving Read and Write Stability

Kumar, Gopavaram Suneel; Mamatha, G.

doi:10.1109/icdsis55133.2022.9915838

Cited by 1 publication

(1 citation statement)

References 12 publications

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“…In this manuscript, SGFinFETs based SRAM cell design under LECTOR technique (SGFinFETs‐SRAM‐LECTOR) is proposed to diminish the LPD and also improves the SNM and PDP 28,29 …”

Section: Proposed Methodologymentioning

confidence: 99%

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Sankranti,

Roji Marjorie

2023

Softw Pract Exp

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Static random‐access memory (SRAM) plays a vital component of digital systems. The main issue of SRAM cells is power leakage, which results in an increase in chip area. Therefore this manuscript proposes a shorted‐gate fin‐type field‐effect transistor based SRAM cell utilizing leakage control transistor technique (SGFinFETs‐SRAM‐LECTOR) for decreasing the leakage power delay by improving the static noise margins (SNMs) together with power delay product (PDP). Here, the SGFinFETs‐SRAM‐LECTOR is primarily applied to stacking enhancement for lessening the leakage power dissipation (LPD). Two more transistors are used in LECTOR for reducing the leakage current with delay, which is based on transistor stacking. LECTOR employs two more transistors that are connected in series between pull‐up and pull‐down networks that means additional SG FinFETs PMOS transistor insertions amongst the pull‐up network and output terminal, additional SG FinFETs NMOS transistor insertions amidst the pull down network and output terminal. These additional transistors can decrease the leakage current. The simulation of the proposed approach is implemented in HSPICE simulation tool. Some metrics are computed to validate the efficacy of the proposed approach. Finally, the proposed technique reaches 11.31%, 51.47%, 45.46% less read delay, 44.44%, 26.33%, 33.45% less write delay, 36.12%, 45.28%, 26.45% less read power, 34.5%, 33.56%, 22.41% less write power, 37.4%, 15.3%, 26.54% high read SNM, 33.67%, 35.8%,12.09% high write SNM when analyzed to the existing models.

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“…In this manuscript, SGFinFETs based SRAM cell design under LECTOR technique (SGFinFETs‐SRAM‐LECTOR) is proposed to diminish the LPD and also improves the SNM and PDP 28,29 …”

Section: Proposed Methodologymentioning

confidence: 99%

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Sankranti,

Roji Marjorie

2023

Softw Pract Exp

View full text Add to dashboard Cite

show abstract

An Efficient 5-Transistor SRAM Cell Design using FNSBS-CNTFET for Improving Read and Write Stability

Cited by 1 publication

References 12 publications

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

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