An efficient algorithm for the physical mapping of clustered task graphs onto multiprocessor architectures

Koziris, Nectarios; Romesis, Michail; Tsanakas, Panayiotis; Παπακωνσταντίνου, Γ.

doi:10.1109/empdp.2000.823437

Cited by 44 publications

(29 citation statements)

References 11 publications

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“…To evaluate our technique, we define a Cost Function (CF), similar to the kind of cost function used in Koziris [5] and Zhonghai [6].…”

Section: Cost Function Formulationmentioning

confidence: 99%

A Generic Graph-Oriented Mapping Strategy for a Honeycomb Topology

Singh¹,

Alle²,

Vardarajan³

et al. 2010

IJCA

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REDEFINE [3] is a polymorphic ASIC, in which arbitrary computational structures on hardware are defined at runtime. The REDEFINE execution fabric comprises Compute Elements (CEs) interconnected by a Honeycomb network, which also serves as the distributed Network-on-chip. Each computational structure is dynamically assigned to a subset of the CEs on the execution fabric by the REDEFINE support logic. A HLL specification of the application is compiled into Hyper Operations (HyperOps) by the REDEFINE compiler [3], where each HyperOp is a set of interacting operations. The compiler also determines partitions of the HyperOps (pHyperOps) that can be assigned to CEs to suitably meet the structural constraints of the execution fabric. In this paper we propose an algorithm to map HyperOps onto Computational Structures. A pHyperOp communication graph (PCG) captures the communication between the various pHyperOps. Through a sequence of transformations, the PCG is transformed into a Cayley tree. The Cayley tree is then overlayed on the Cayley graph to form a computational structure. The proposed mapping algorithm offers a solution that incurs a penalty 18% on average over that of the optimal.

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“…To evaluate our technique, we define a Cost Function (CF), similar to the kind of cost function used in Koziris [5] and Zhonghai [6].…”

Section: Cost Function Formulationmentioning

confidence: 99%

A Generic Graph-Oriented Mapping Strategy for a Honeycomb Topology

Singh¹,

Alle²,

Vardarajan³

et al. 2010

IJCA

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“…Application mapping problem is NP-hard [11]. This paper explores a meta-heuristic, Discrete Particle Swarm Optimization (DPSO), to perform application mapping onto BFT-based NoCs.…”

Section: Introductionmentioning

confidence: 99%

Application Mapping onto Butterfly-Fat-Tree based Network-on-Chip using Discrete Particle Swarm Optimization

Sahu¹,

Manna²,

Chattopadhyay³

2015

IJCA

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This paper addresses the problem of application mapping onto Butterfly-Fat-Tree (BFT) based Network-on-Chip design. It proposes a new mapping technique based on discrete Particle Swarm Optimization (PSO) to map the cores of the core graph to the routers. The basic PSO has been augmented by running multiple PSO and deterministically generating a part of the initial population for PSO. The mapping results have been compared with well-known techniques reported in the literature for a number of benchmark applications. The reported strategy produces results superior to those obtained via existing approaches within a reasonable CPU time. KeywordsApplication mapping, Network-on-Chip, System-on-Chip, Butterfly-Fat-Tree, Discrete Particle Swarm Optimization INTRODUCTIONNetwork-on-Chip (NoC) has evolved as a viable strategy to implement Intellectual Property (IP) core based System-onChip (SoC) designs. It solves the traditional problems of bandwidth limitations of bus-based SoC design by providing an on-chip network fabric consisting of routers connected in a certain topology. Conventional data signal exchanges are replaced by message passing between the cores through the router fabric [1]- [4]. A major challenge in NoC based system design is to associate the IP cores implementing tasks of an application with routers. This is commonly known as the process of application mapping. This has got a very significant role to play in performance of the overall system as it directly influences the communication time, the required link bandwidth, the admissible delay of the router, and energy consumption of the whole NoC [5], [6]. Furthermore, these requirements vary from one application domain to another. For example, while multimedia applications require high bandwidth, real time systems require guaranteed delay, and portable devices require low power consumption. Most of the application mapping algorithms reported in the literature assumes a mesh-connected router fabric for the NoC. In [6]- [10], authors have proposed many topologies for NoC. Butterfly-Fat-Tree (BFT) enjoys several advantages over other topologies [7], [10]. The BFT topology can be easily implemented inside chips. It has the advantage of having small diameter as well as symmetric structure. There are various versions of the networks connected in the tree like architecture and most of them have recursive structures. The wire routing is also simpler. In chip design, for same number of cores, the area occupied by BFT is less than the mesh topology. These characteristics make BFT a popular scheme for interconnecting IPs [7], [10]. In [7] stage. This ensures faster convergence and improved quality of solution for the successive stages.3. For any stage of PSO, the initial population generation is not fully random. A good number of particles have been created using a heuristic. This has enabled our PSO to explore the promising regions of search space much better.4. The communication cost metric values of the mapping solutions of our approach have been compared ...

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“…A distributed OO application consists mainly of a set of interacting objects; each one runs on a separate computer within a network system. There have been a large number of projects related to the use of object-oriented approaches for the design of problem solving environments for complex applications in various scientific fields [7]. The object model and distributed technologies are being amalgamated [8].…”

Section: Introductionmentioning

confidence: 99%