An Efficient FPGA Implementation of Versatile Video Coding Intra Prediction

Abstract

Versatile Video Coding (VVC) is a new international video compression standard offering much better compression efficiency than previous video compression standards at the expense of much higher computational complexity. In this paper, an efficient FPGA implementation of VVC intra prediction for angular prediction modes of 4x4, 8x8, 16x16 and 32x32 prediction unit sizes is proposed. In the proposed FPGA implementation, four constant multiplications used in one intra angular prediction equation are implemented using two DSP blocks and two adders in FPGA. The proposed FPGA implementation of VVC intra prediction, in the worst case, can process 34 full HD (1920x1080) frames per second.

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

“…Azgin et al [74] designed a hardware architecture for the VVC intra prediction encoder. This architecture encompasses only the 65 angular prediction modes and square-shaped blocks with sizes ranging from 4×4 to 32×32.…”

Modern Video Coding: Methods, Challenges and Systems

“…Thus, a total of 17 different block sizes are supported by the VVC intra prediction. Although this standard presents an increased complexity for intra operations, there is only one work that proposes specific hardware architectures for this module [51].…”

“…Since this standard is still very recent, a few works focus on hardware solutions for the VVC intra prediction step. In [51], the authors propose a FPGA architecture for this module, supporting square blocks from size 4x4 to 32x32, using only two DSP blocks and two adders to implement the operations of intra modes. The architecture processes 34fps at HD 1080p resolution.…”