An efficient high speed and low power voltage-level shifter

Rezaei, Neda; Mirhassani, Mitra

doi:10.1016/j.aeue.2021.153857

Cited by 4 publications

(1 citation statement)

References 21 publications

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“…The utilization of efficient and energy-saving techniques [18][19][20][21] based on 180 nm technology and subsequent advancements has facilitated the improvement of chip area. Although they possess significant advantages in terms of space and energy, they may not be well suited for applications that require low latency.…”

Section: Introduction and Literature Surveymentioning

confidence: 99%

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Sudhakar,

Stan

2023

Electronics

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The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.

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Section: Introduction and Literature Surveymentioning

confidence: 99%

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Sudhakar,

Stan

2023

Electronics

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A low quiescent current power-on-reset circuit with configurable trip voltage

You¹,

Zhou

Qiao

2022

AEU - International Journal of Electronics and Communications

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High-speed voltage level-up shifter with wide range conversion for system-on-chip applications

Sudhakar

2024

Eng. Res. Express

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The purpose of this investigation is to demonstrate a level shifter circuit that enhances voltage switching capacity while simultaneously reducing latency by employing a cascaded current mirror, input, and output inverters. We improved our design using multi-threshold Complementary metal oxide semiconductor (MTCMOS) technology by adding stackable transistors, super-cutoff mechanisms, and cascaded techniques. The level shifting between voltage ranges of 0.3 V and 2.0 V is accomplished by the proposed level shifter. Our design has been fine-tuned to meet the needs of system-on-chip applications by meticulously optimizing performance characteristics like energy usage, latency, and space utilization. The proposed level shifter has an area of 6.936 µm2 and a power consumption of 17 nW, with a delay of 90.64 ps. The proposed work has been done on the Cadence Virtuoso Tool using 45 nm technology. Our suggested level shifter is more effective than earlier methods in terms of latency and conversion range. In addition to delivering considerable reductions in space and power consumption, the suggested design promises a 50-fold increase in operating speed.

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An efficient high speed and low power voltage-level shifter

Cited by 4 publications

References 21 publications

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

A low quiescent current power-on-reset circuit with configurable trip voltage

High-speed voltage level-up shifter with wide range conversion for system-on-chip applications

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