An Efficient VLSI Architecture for Convolution Based DWT Using MAC

Basiri, M. Mohamed Asan; Sk, Noor Mahammad

doi:10.1109/vlsid.2018.75

Cited by 7 publications

(3 citation statements)

References 25 publications

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“…Lifting-based hardware architectures [ 33 , 34 , 35 , 36 , 37 , 38 ] are usually simpler, have lower computational complexity and utilize less amount of logic and memory resources. The most efficient hardware architectures of the 1-D DWT and 2-D DWT are described in [ 28 ] and [ 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 53 , 54 , 55 , 56 , 57 , 58 , 59 , 60 ]. The concept of the proposed 2-D DWT with 5/3 filters and its hardware architecture are presented in [ 61 , 62 , 63 ].…”

Section: Introductionmentioning

confidence: 99%

Digital Image Decoder for Efficient Hardware Implementation

Savić

Prokin

Rajović

et al. 2022

Sensors

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Increasing the resolution of digital images and the frame rate of video sequences leads to an increase in the amount of required logical and memory resources necessary for digital image and video decompression. Therefore, the development of new hardware architectures for digital image decoder with a reduced amount of utilized logical and memory resources become a necessity. In this paper, a digital image decoder for efficient hardware implementation, has been presented. Each block of the proposed digital image decoder has been described. Entropy decoder, decoding probability estimator, dequantizer and inverse subband transformer (parts of the digital image decoder) have been developed in such way which allows efficient hardware implementation with reduced amount of utilized logic and memory resources. It has been shown that proposed hardware realization of inverse subband transformer requires 20% lower memory capacity and uses less logic resources compared with the best state-of-the-art realizations. The proposed digital image decoder has been implemented in a low-cost FPGA device and it has been shown that it requires at least 32% less memory resources in comparison to the other state-of-the-art decoders which can process high-definition frame size. The proposed solution also requires effectively lower memory size than state-of-the-art architectures which process frame size or tile size smaller than high-definition size. The presented digital image decoder has maximum operating frequency comparable with the highest maximum operating frequencies among the state-of-the-art solutions.

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Section: Introductionmentioning

confidence: 99%

Digital Image Decoder for Efficient Hardware Implementation

Savić

Prokin

Rajović

et al. 2022

Sensors

View full text Add to dashboard Cite

show abstract

“…Lossy compression methods, especially when used at low bit rates, introduce compression artefacts. In general, VLSI architecture for DWT is classified into three categories, (i) convolution based [2]; (ii) lifting based [3, 4]; and (iii) B‐spline based.…”

Section: Introductionmentioning

confidence: 99%

Efficient VLSI architectures of lifting based 3D discrete wavelet transform

Basiri

2020

IET Computers & Digital Techniques

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“…In this work, we preferred the conventional convolutionbased DWT implementation over the LS for the following reasons. In LS, as the critical path delay (CPD) increases, the energy per operation increases and the operating frequency decreases [10]. In [11,12], the authors found constant bit widths [20], whereas the GE require more computational resources due to a larger search space [22].…”

Section: Introductionmentioning

confidence: 99%

An optimized two-level discrete wavelet implementation using residue number system

Alzaq

Ustundag

2018

EURASIP J. Adv. Signal Process.

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Using discrete wavelet transform (DWT) in high-speed signal processing applications imposes a high degree of caution to hardware resource availability, latency and power consumption. In this paper, we investigated the design and implementation aspects of a multiplier-free two-level DWT by using residue number system (RNS). The proposed two-level takes the advantage of performing the multiplication operations using only the memory without involving special multiplier units, which preserves valuable resources for other critical tasks within the FPGA. The design was implemented and synthesized in ZYNQ ZC706 development kit, taking advantage of embedded block RAMs (BRAMs). The results of the overall experimentations showed that there is a considerable improve in the proposed two-level DWT design with regard to latency and peak signal-to-noise ratio (PSNR) precision value in the final output.

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An Efficient VLSI Architecture for Convolution Based DWT Using MAC

Cited by 7 publications

References 25 publications

Digital Image Decoder for Efficient Hardware Implementation

Digital Image Decoder for Efficient Hardware Implementation

Efficient VLSI architectures of lifting based 3D discrete wavelet transform

An optimized two-level discrete wavelet implementation using residue number system

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