An embedded system for real-time traffic sign recognizing

Souki, M.A.; Boussaid, Lotfi; Abid, Mohamed

doi:10.1109/idt.2008.4802512

Cited by 18 publications

(12 citation statements)

References 9 publications

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“…A hardware/software co-design implementation of traffic sign recognition is presented in [5]. A soft core processor, Nios II, is implemented on Altera FPGA chip using a CYCLONE II DE2 Board.…”

Section: Detection Of Circlesmentioning

confidence: 99%

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Memory efficient FPGA implementation of hough transform for line and circle detection

Elhossini

Moussa

2012

2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

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Hough transform (HT) is a widely used algorithm in machine vision systems. In this paper, a memory efficient architecture for implementing HT on FPGAs is presented. The proposed architecture enables storing the HT space on the FPGA's memory blocks with no need for accessing external memory while processing large size images in real-time with high frame rate. It can be used for both line and circle detection. Results show very good accuracy with images processed at 30 fps frame rate and image size of 800 × 600. This compares favourably with other reported architectures in the literature. Index Terms-Hough Transform, FPGA, Computer vision 1. INTRODUCTIONIn the past decade, the use of reconfigurable hardware, and particularly FPGAs, has increased dramatically in the field of image processing and machine vision systems Hough Transform (HT) is commonly used for detecting straight lines in images [1]. Implementing this algorithm on FPGAs is challenging due to the high demand on memory storage and the complexity of the algorithm. Normally external memory is used to store the HT data [2,3,4]. This introduces limitations on the bandwidth of the data transfer which leads to limiting the size of the image window and frame rate. This is particularly the case when HT is extended to detect circles and other shapes [4,5,6]. In this paper we present an architecture to implement the HT for both straight lines and circles. It employs an efficient memory design that eliminates the need to use external memory and allows processing of large image sizes at a high frame rate. This paper is organized as follows: Section 2 covers background material about the HT while Section 3 surveys related work. Section 4 introduces the proposed architecture and FPGA implementation. Section 5 presents testing, results, and discussion. Finally section 6 concludes the paper. BACKGROUNDHT works on the contour points resulting from the edge detection process. Each contour point contributes in a voting process for several instances of the object being detected. For each instance a memory location is used to store its vote. The memory used to store the votes of all instances of the object is called HT space. The local minima in the HT space represents the object that received the maximum number of votes. A parameterized model of the object should be provided to relate contour pixels position to the object template. Straight line equation can be expressed in a parameterized form asThe HT space constructed using Equation 1 is a two dimensional space where each point in the space represents a line that corresponds to a single value of and . Each new pixel is used to compute the value of using the position of the pixel (x, y) for each angle . The vote for the line defined by and is then incremented. The HT space should be sampled to allow a limited memory size to store the voting results. Sampling the HT space affects the accuracy of the resulting transform, but is essential for efficient hardware implementation. HT can be modified to detect other shapes by mo...

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Section: Detection Of Circlesmentioning

confidence: 99%

“…This introduces limitations on the bandwidth of the data transfer which leads to limiting the size of the image window and frame rate. This is particularly the case when HT is extended to detect circles and other shapes [4,5,6]. In this paper we present an architecture to implement the HT for both straight lines and circles.…”

mentioning

confidence: 99%

Memory efficient FPGA implementation of hough transform for line and circle detection

Elhossini

Moussa

2012

2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

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“…In These enhancements make RGB color space more suitable for segmentation than it actually is. However, the most important reason of its preference is to get rid of computation burden of conversion [24]. On the other hand, Hue Saturation Intensity (HSI) color space shows better performance against illumination changes [25].…”

Section: Background Of Traffic Sign Detection and Recognitionmentioning

confidence: 99%

“…Höferlin and Zimmermann do not use image as input of NN directly [24]. First, SIFT is applied to detected sign.…”

Section: Background Of Traffic Sign Detection and Recognitionmentioning

confidence: 99%

Real-time Traffic Sign detection and Recognition on FPGA

Yalçın

Irmak

Bulut

et al. 2013

2013 21st Signal Processing and Communications Applications Conference (SIU)

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In this thesis, an embedded system for traffic sign detection and recognition is proposed. Proposed system is first designed in MATLAB and optimized. After optimization process, system design is transferred to FPGA and Virtex-V FX70 FPGA is selected for implementation platform. 640x480 sized image in RGB format is sent to FPGA system via computer interface. This image is segmented for red, blue, and yellow colors. Red and blue color maps are divided into 8x8 sub-blocks. Yellow color map is divided into 32x32 sub-blocks. After that, blocks which have more than 30 % valid pixels are marked as valid. Red and blue maps are converted into 80x60 and blobs are detected in these maps. Size of the detected blob is examined first and appropriate sized regions are marked as valid. Next, to be marked as traffic sign, valid regions are expected to meet one of the three conditions: Vertical neighboring, yellow sign neighboring and pole detection below the region. Regions marked as traffic sign are interpolated to 60x60. Color segmentation operation is applied to these regions and edges are extracted in segmented images. Hough Transform is applied to edge images and contour information is extracted. Finally, Informative Pixel Percentage (IPP) operation is applied to inner region of the signs and results are obtained. FPGA system is composed of two sub-parts: Processor system and hardware (logic) system. Color segmentation, region detection and pole detection modules are implemented in hardware system. Rest of the operations is implemented in the processor system. To test success of the implemented system, 137 images, which include 162 traffic signs, are sent to this system and 90.1 % detection and 90.4 % recognition rates are achieved.

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“…The interest in ADAS is continuously increasing in the automotive field to improve vehicle safety and comfort [1][2][3][4][5][6][7][8][9][10]. Over the world, traffic crashes kill more than 1 million of people each year [4].…”

Section: Introductionmentioning

confidence: 99%

Hardware accelerator IP cores for real time Radar and camera-based ADAS

Saponara

2016

J Real-Time Image Proc

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The paper presents the design of HDL macrocells, working as hardware accelerators to achieve real time processing of some key functions of Advanced Driver Assistance Systems (ADAS). Particularly, the macrocells process in real time images from Radar and video-camera sensors implementing computing-intensive operations such as: pixel-level filtering, correction of distortions in large field-of-view cameras, multi-camera image fusion for panoramic view of car’s surround, traffic and road signs recognition, detection of obstacles for collision avoidance, and estimation of their distance and speed. The HDL macrocells are fully configurable and are synthesized in low-cost Artix-7 FPGA family, satisfying automotive-grade requirements. They can be integrated as accelerators in embedded hardware–software platforms to build a complete ADAS solution. To this aim, the macrocells have been synthesized also in a Zynq FPSoC. With respect to the state of the art, the proposed macrocells stand for their low-power and real time performanc

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An embedded system for real-time traffic sign recognizing

Cited by 18 publications

References 9 publications

Memory efficient FPGA implementation of hough transform for line and circle detection

Memory efficient FPGA implementation of hough transform for line and circle detection

Real-time Traffic Sign detection and Recognition on FPGA

Hardware accelerator IP cores for real time Radar and camera-based ADAS

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